Commit fdf84f10 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher

drm/amd/display: Update DCN35 watermarks

[Why & How]
Update to the new values per HW team request. Affects both stutter
and z8.
Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Acked-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b9eab9e0
...@@ -443,32 +443,32 @@ static struct wm_table ddr5_wm_table = { ...@@ -443,32 +443,32 @@ static struct wm_table ddr5_wm_table = {
.wm_inst = WM_A, .wm_inst = WM_A,
.wm_type = WM_TYPE_PSTATE_CHG, .wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72, .pstate_latency_us = 11.72,
.sr_exit_time_us = 9, .sr_exit_time_us = 14.0,
.sr_enter_plus_exit_time_us = 11, .sr_enter_plus_exit_time_us = 16.0,
.valid = true, .valid = true,
}, },
{ {
.wm_inst = WM_B, .wm_inst = WM_B,
.wm_type = WM_TYPE_PSTATE_CHG, .wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72, .pstate_latency_us = 11.72,
.sr_exit_time_us = 9, .sr_exit_time_us = 14.0,
.sr_enter_plus_exit_time_us = 11, .sr_enter_plus_exit_time_us = 16.0,
.valid = true, .valid = true,
}, },
{ {
.wm_inst = WM_C, .wm_inst = WM_C,
.wm_type = WM_TYPE_PSTATE_CHG, .wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72, .pstate_latency_us = 11.72,
.sr_exit_time_us = 9, .sr_exit_time_us = 14.0,
.sr_enter_plus_exit_time_us = 11, .sr_enter_plus_exit_time_us = 16.0,
.valid = true, .valid = true,
}, },
{ {
.wm_inst = WM_D, .wm_inst = WM_D,
.wm_type = WM_TYPE_PSTATE_CHG, .wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72, .pstate_latency_us = 11.72,
.sr_exit_time_us = 9, .sr_exit_time_us = 14.0,
.sr_enter_plus_exit_time_us = 11, .sr_enter_plus_exit_time_us = 16.0,
.valid = true, .valid = true,
}, },
} }
...@@ -480,32 +480,32 @@ static struct wm_table lpddr5_wm_table = { ...@@ -480,32 +480,32 @@ static struct wm_table lpddr5_wm_table = {
.wm_inst = WM_A, .wm_inst = WM_A,
.wm_type = WM_TYPE_PSTATE_CHG, .wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333, .pstate_latency_us = 11.65333,
.sr_exit_time_us = 11.5, .sr_exit_time_us = 14.0,
.sr_enter_plus_exit_time_us = 14.5, .sr_enter_plus_exit_time_us = 16.0,
.valid = true, .valid = true,
}, },
{ {
.wm_inst = WM_B, .wm_inst = WM_B,
.wm_type = WM_TYPE_PSTATE_CHG, .wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333, .pstate_latency_us = 11.65333,
.sr_exit_time_us = 11.5, .sr_exit_time_us = 14.0,
.sr_enter_plus_exit_time_us = 14.5, .sr_enter_plus_exit_time_us = 16.0,
.valid = true, .valid = true,
}, },
{ {
.wm_inst = WM_C, .wm_inst = WM_C,
.wm_type = WM_TYPE_PSTATE_CHG, .wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333, .pstate_latency_us = 11.65333,
.sr_exit_time_us = 11.5, .sr_exit_time_us = 14.0,
.sr_enter_plus_exit_time_us = 14.5, .sr_enter_plus_exit_time_us = 16.0,
.valid = true, .valid = true,
}, },
{ {
.wm_inst = WM_D, .wm_inst = WM_D,
.wm_type = WM_TYPE_PSTATE_CHG, .wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333, .pstate_latency_us = 11.65333,
.sr_exit_time_us = 11.5, .sr_exit_time_us = 14.0,
.sr_enter_plus_exit_time_us = 14.5, .sr_enter_plus_exit_time_us = 16.0,
.valid = true, .valid = true,
}, },
} }
......
...@@ -164,10 +164,10 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = { ...@@ -164,10 +164,10 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {
}, },
}, },
.num_states = 5, .num_states = 5,
.sr_exit_time_us = 9.0, .sr_exit_time_us = 14.0,
.sr_enter_plus_exit_time_us = 11.0, .sr_enter_plus_exit_time_us = 16.0,
.sr_exit_z8_time_us = 50.0, /*changed from 442.0*/ .sr_exit_z8_time_us = 525.0,
.sr_enter_plus_exit_z8_time_us = 50.0,/*changed from 560.0*/ .sr_enter_plus_exit_z8_time_us = 715.0,
.fclk_change_latency_us = 20.0, .fclk_change_latency_us = 20.0,
.usr_retraining_latency_us = 2, .usr_retraining_latency_us = 2,
.writeback_latency_us = 12.0, .writeback_latency_us = 12.0,
......
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