Commit ffd0a782 authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman

staging: comedi: ni_stc.h: remove NI_PRIVATE_COMMON macro

This macro is used to create the private data structure that is used by
the ni_atmio, ni_mio_cs, and ni_pcimio drivers. These drivers all include
the ni_mio_common.c source to provide most of the driver functionality.

The only driver specific information needed to convert the macro into a
proper struct definition is the MAX_N_CALDACS define. This define is used
to size a couple array members in the struct. The ni_atmio and ni_mio_cs
drivers both define MAX_N_CALDACS as 32. The ni_pcimio driver defines it
as (16+16+2). The ni_mio_common file only uses this define to sanity check
that the struct members are large enough for the number of channels in
the calibration subdevice.

Move the MAX_N_CALDACS define to ni_stc.h and set it to the largest number
of caldacs (34).

The ni_atmio and ni_mio_cs drivers also add one additional member to the
private data struct before using the NI_PRIVATE_COMMON macro.

For the ni_atmio driver, the struct pnp_dev pointer can be saved in the
comedi_device as the 'hw_dev'. The (*detach) of this driver can then use
to_pnp_dev() to get it back when detaching the pnp device.

In the ni_mio_cs driver, the struct pcmia_device pointer is not used so
it can simply be removed.

The NI_PRIVATE_COMMON macro can then be converted into a proper struct
definition.
Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent f40c283a
......@@ -107,8 +107,6 @@ are not supported.
#define NI_SIZE 0x20
#define MAX_N_CALDACS 32
static const struct ni_board_struct ni_boards[] = {
{.device_id = 44,
.isapnp_id = 0x0000, /* XXX unknown */
......@@ -272,12 +270,6 @@ static const int ni_irqpin[] = {
#define NI_E_IRQ_FLAGS 0
struct ni_private {
struct pnp_dev *isapnp_dev;
NI_PRIVATE_COMMON
};
/* How we access registers */
#define ni_writel(a, b) (outl((a), (b)+dev->iobase))
......@@ -428,7 +420,7 @@ static int ni_atmio_attach(struct comedi_device *dev,
iobase = pnp_port_start(isapnp_dev, 0);
irq = pnp_irq(isapnp_dev, 0);
devpriv->isapnp_dev = isapnp_dev;
comedi_set_hw_dev(dev, &isapnp_dev->dev);
}
ret = comedi_request_region(dev, iobase, NI_SIZE);
......@@ -477,12 +469,14 @@ static int ni_atmio_attach(struct comedi_device *dev,
static void ni_atmio_detach(struct comedi_device *dev)
{
struct ni_private *devpriv = dev->private;
struct pnp_dev *isapnp_dev;
mio_common_detach(dev);
comedi_legacy_detach(dev);
if (devpriv->isapnp_dev)
pnp_device_detach(devpriv->isapnp_dev);
isapnp_dev = dev->hw_dev ? to_pnp_dev(dev->hw_dev) : NULL;
if (isapnp_dev)
pnp_device_detach(isapnp_dev);
}
static struct comedi_driver ni_atmio_driver = {
......
......@@ -56,8 +56,6 @@ See the notes in the ni_atmio.o driver.
#define NI_SIZE 0x20
#define MAX_N_CALDACS 32
static const struct ni_board_struct ni_boards[] = {
{
.device_id = 0x010d,
......@@ -143,12 +141,6 @@ static const struct ni_board_struct ni_boards[] = {
#define IRQ_POLARITY 1
struct ni_private {
struct pcmcia_device *link;
NI_PRIVATE_COMMON};
/* How we access registers */
#define ni_writel(a, b) (outl((a), (b)+dev->iobase))
......
......@@ -121,8 +121,6 @@ SCXI is probably broken for m-series boards.
#define PCIMIO 1
#undef ATMIO
#define MAX_N_CALDACS (16+16+2)
#define DRV_NAME "ni_pcimio"
/* These are not all the possible ao ranges for 628x boards.
......@@ -1044,9 +1042,6 @@ static const struct ni_board_struct ni_boards[] = {
},
};
struct ni_private {
NI_PRIVATE_COMMON};
/* How we access registers */
#define ni_writel(a, b) (writel((a), devpriv->mite->daq_io_addr + (b)))
......
......@@ -1416,92 +1416,94 @@ struct ni_board_struct {
enum caldac_enum caldac[3];
};
#define MAX_N_AO_CHAN 8
#define NUM_GPCT 2
#define NI_PRIVATE_COMMON \
uint16_t (*stc_readw)(struct comedi_device *dev, int register); \
uint32_t (*stc_readl)(struct comedi_device *dev, int register); \
void (*stc_writew)(struct comedi_device *dev, uint16_t value, int register); \
void (*stc_writel)(struct comedi_device *dev, uint32_t value, int register); \
\
unsigned short dio_output; \
unsigned short dio_control; \
int ao0p, ao1p; \
int lastchan; \
int last_do; \
int rt_irq; \
int irqmask; \
int aimode; \
int ai_continuous; \
int blocksize; \
int n_left; \
unsigned int ai_calib_source; \
unsigned int ai_calib_source_enabled; \
spinlock_t window_lock; \
spinlock_t soft_reg_copy_lock; \
spinlock_t mite_channel_lock; \
\
int changain_state; \
unsigned int changain_spec; \
\
unsigned int caldac_maxdata_list[MAX_N_CALDACS]; \
unsigned short ao[MAX_N_AO_CHAN]; \
unsigned short caldacs[MAX_N_CALDACS]; \
\
unsigned short ai_cmd2; \
\
unsigned short ao_conf[MAX_N_AO_CHAN]; \
unsigned short ao_mode1; \
unsigned short ao_mode2; \
unsigned short ao_mode3; \
unsigned short ao_cmd1; \
unsigned short ao_cmd2; \
unsigned short ao_cmd3; \
unsigned short ao_trigger_select; \
\
struct ni_gpct_device *counter_dev; \
unsigned short an_trig_etc_reg; \
\
unsigned ai_offset[512]; \
\
unsigned long serial_interval_ns; \
unsigned char serial_hw_mode; \
unsigned short clock_and_fout; \
unsigned short clock_and_fout2; \
\
unsigned short int_a_enable_reg; \
unsigned short int_b_enable_reg; \
unsigned short io_bidirection_pin_reg; \
unsigned short rtsi_trig_direction_reg; \
unsigned short rtsi_trig_a_output_reg; \
unsigned short rtsi_trig_b_output_reg; \
unsigned short pfi_output_select_reg[NUM_PFI_OUTPUT_SELECT_REGS]; \
unsigned short ai_ao_select_reg; \
unsigned short g0_g1_select_reg; \
unsigned short cdio_dma_select_reg; \
\
unsigned clock_ns; \
unsigned clock_source; \
\
unsigned short atrig_mode; \
unsigned short atrig_high; \
unsigned short atrig_low; \
\
unsigned short pwm_up_count; \
unsigned short pwm_down_count; \
\
unsigned short ai_fifo_buffer[0x2000]; \
uint8_t eeprom_buffer[M_SERIES_EEPROM_SIZE]; \
uint32_t serial_number; \
\
struct mite_struct *mite; \
struct mite_channel *ai_mite_chan; \
struct mite_channel *ao_mite_chan;\
struct mite_channel *cdo_mite_chan;\
struct mite_dma_descriptor_ring *ai_mite_ring; \
struct mite_dma_descriptor_ring *ao_mite_ring; \
struct mite_dma_descriptor_ring *cdo_mite_ring; \
#define MAX_N_CALDACS 34
#define MAX_N_AO_CHAN 8
#define NUM_GPCT 2
struct ni_private {
uint16_t (*stc_readw)(struct comedi_device *, int reg);
uint32_t (*stc_readl)(struct comedi_device *, int reg);
void (*stc_writew)(struct comedi_device *, uint16_t value, int reg);
void (*stc_writel)(struct comedi_device *, uint32_t value, int reg);
unsigned short dio_output;
unsigned short dio_control;
int ao0p, ao1p;
int lastchan;
int last_do;
int rt_irq;
int irqmask;
int aimode;
int ai_continuous;
int blocksize;
int n_left;
unsigned int ai_calib_source;
unsigned int ai_calib_source_enabled;
spinlock_t window_lock;
spinlock_t soft_reg_copy_lock;
spinlock_t mite_channel_lock;
int changain_state;
unsigned int changain_spec;
unsigned int caldac_maxdata_list[MAX_N_CALDACS];
unsigned short ao[MAX_N_AO_CHAN];
unsigned short caldacs[MAX_N_CALDACS];
unsigned short ai_cmd2;
unsigned short ao_conf[MAX_N_AO_CHAN];
unsigned short ao_mode1;
unsigned short ao_mode2;
unsigned short ao_mode3;
unsigned short ao_cmd1;
unsigned short ao_cmd2;
unsigned short ao_cmd3;
unsigned short ao_trigger_select;
struct ni_gpct_device *counter_dev;
unsigned short an_trig_etc_reg;
unsigned ai_offset[512];
unsigned long serial_interval_ns;
unsigned char serial_hw_mode;
unsigned short clock_and_fout;
unsigned short clock_and_fout2;
unsigned short int_a_enable_reg;
unsigned short int_b_enable_reg;
unsigned short io_bidirection_pin_reg;
unsigned short rtsi_trig_direction_reg;
unsigned short rtsi_trig_a_output_reg;
unsigned short rtsi_trig_b_output_reg;
unsigned short pfi_output_select_reg[NUM_PFI_OUTPUT_SELECT_REGS];
unsigned short ai_ao_select_reg;
unsigned short g0_g1_select_reg;
unsigned short cdio_dma_select_reg;
unsigned clock_ns;
unsigned clock_source;
unsigned short atrig_mode;
unsigned short atrig_high;
unsigned short atrig_low;
unsigned short pwm_up_count;
unsigned short pwm_down_count;
unsigned short ai_fifo_buffer[0x2000];
uint8_t eeprom_buffer[M_SERIES_EEPROM_SIZE];
uint32_t serial_number;
struct mite_struct *mite;
struct mite_channel *ai_mite_chan;
struct mite_channel *ao_mite_chan;
struct mite_channel *cdo_mite_chan;
struct mite_dma_descriptor_ring *ai_mite_ring;
struct mite_dma_descriptor_ring *ao_mite_ring;
struct mite_dma_descriptor_ring *cdo_mite_ring;
struct mite_dma_descriptor_ring *gpct_mite_ring[NUM_GPCT];
};
#endif /* _COMEDI_NI_STC_H */
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