Commit fff4a87f authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'tegra-for-5.8-firmware-v2' of...

Merge tag 'tegra-for-5.8-firmware-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

firmware: tegra: Changes for v5.8-rc1

This contains a change that makes the BPMP driver a regular driver,
which fixes some weird suspend/resume ordering issues. Another fix is
also included to implement another way of enabling the L2 cache after
LP2 suspend.

* tag 'tegra-for-5.8-firmware-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  firmware: tegra: Defer BPMP probe if shared memory not available
  firmware: tf: Different way of L2 cache enabling after LP2 suspend
  firmware: tegra: Make BPMP a regular driver

Link: https://lore.kernel.org/r/20200515145311.1580134-6-thierry.reding@gmail.com
Link: https://lore.kernel.org/r/20200522142846.2376224-1-thierry.reding@gmail.comSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 8222d4c3 10b20066
...@@ -176,7 +176,7 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) ...@@ -176,7 +176,7 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp)
priv->tx.pool = of_gen_pool_get(bpmp->dev->of_node, "shmem", 0); priv->tx.pool = of_gen_pool_get(bpmp->dev->of_node, "shmem", 0);
if (!priv->tx.pool) { if (!priv->tx.pool) {
dev_err(bpmp->dev, "TX shmem pool not found\n"); dev_err(bpmp->dev, "TX shmem pool not found\n");
return -ENOMEM; return -EPROBE_DEFER;
} }
priv->tx.virt = gen_pool_dma_alloc(priv->tx.pool, 4096, &priv->tx.phys); priv->tx.virt = gen_pool_dma_alloc(priv->tx.pool, 4096, &priv->tx.phys);
...@@ -188,7 +188,7 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) ...@@ -188,7 +188,7 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp)
priv->rx.pool = of_gen_pool_get(bpmp->dev->of_node, "shmem", 1); priv->rx.pool = of_gen_pool_get(bpmp->dev->of_node, "shmem", 1);
if (!priv->rx.pool) { if (!priv->rx.pool) {
dev_err(bpmp->dev, "RX shmem pool not found\n"); dev_err(bpmp->dev, "RX shmem pool not found\n");
err = -ENOMEM; err = -EPROBE_DEFER;
goto free_tx; goto free_tx;
} }
......
...@@ -6,6 +6,7 @@ ...@@ -6,6 +6,7 @@
#include <linux/clk/tegra.h> #include <linux/clk/tegra.h>
#include <linux/genalloc.h> #include <linux/genalloc.h>
#include <linux/mailbox_client.h> #include <linux/mailbox_client.h>
#include <linux/module.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/of_device.h> #include <linux/of_device.h>
...@@ -869,12 +870,8 @@ static struct platform_driver tegra_bpmp_driver = { ...@@ -869,12 +870,8 @@ static struct platform_driver tegra_bpmp_driver = {
.name = "tegra-bpmp", .name = "tegra-bpmp",
.of_match_table = tegra_bpmp_match, .of_match_table = tegra_bpmp_match,
.pm = &tegra_bpmp_pm_ops, .pm = &tegra_bpmp_pm_ops,
.suppress_bind_attrs = true,
}, },
.probe = tegra_bpmp_probe, .probe = tegra_bpmp_probe,
}; };
builtin_platform_driver(tegra_bpmp_driver);
static int __init tegra_bpmp_init(void)
{
return platform_driver_register(&tegra_bpmp_driver);
}
core_initcall(tegra_bpmp_init);
...@@ -19,6 +19,7 @@ ...@@ -19,6 +19,7 @@
#define TF_CACHE_ENABLE 1 #define TF_CACHE_ENABLE 1
#define TF_CACHE_DISABLE 2 #define TF_CACHE_DISABLE 2
#define TF_CACHE_REENABLE 4
#define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200 #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
...@@ -29,6 +30,7 @@ ...@@ -29,6 +30,7 @@
#define TF_CPU_PM_S1 0xffffffe4 #define TF_CPU_PM_S1 0xffffffe4
#define TF_CPU_PM_S1_NOFLUSH_L2 0xffffffe7 #define TF_CPU_PM_S1_NOFLUSH_L2 0xffffffe7
static unsigned long tf_idle_mode = TF_PM_MODE_NONE;
static unsigned long cpu_boot_addr; static unsigned long cpu_boot_addr;
static void tf_generic_smc(u32 type, u32 arg1, u32 arg2) static void tf_generic_smc(u32 type, u32 arg1, u32 arg2)
...@@ -85,25 +87,40 @@ static int tf_prepare_idle(unsigned long mode) ...@@ -85,25 +87,40 @@ static int tf_prepare_idle(unsigned long mode)
cpu_boot_addr); cpu_boot_addr);
break; break;
case TF_PM_MODE_NONE:
break;
default: default:
return -EINVAL; return -EINVAL;
} }
tf_idle_mode = mode;
return 0; return 0;
} }
#ifdef CONFIG_CACHE_L2X0 #ifdef CONFIG_CACHE_L2X0
static void tf_cache_write_sec(unsigned long val, unsigned int reg) static void tf_cache_write_sec(unsigned long val, unsigned int reg)
{ {
u32 l2x0_way_mask = 0xff; u32 enable_op, l2x0_way_mask = 0xff;
switch (reg) { switch (reg) {
case L2X0_CTRL: case L2X0_CTRL:
if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_ASSOCIATIVITY_16) if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_ASSOCIATIVITY_16)
l2x0_way_mask = 0xffff; l2x0_way_mask = 0xffff;
switch (tf_idle_mode) {
case TF_PM_MODE_LP2:
enable_op = TF_CACHE_REENABLE;
break;
default:
enable_op = TF_CACHE_ENABLE;
break;
}
if (val == L2X0_CTRL_EN) if (val == L2X0_CTRL_EN)
tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_ENABLE, tf_generic_smc(TF_CACHE_MAINT, enable_op,
l2x0_saved_regs.aux_ctrl); l2x0_saved_regs.aux_ctrl);
else else
tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_DISABLE, tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_DISABLE,
......
...@@ -32,6 +32,7 @@ ...@@ -32,6 +32,7 @@
#define TF_PM_MODE_LP1_NO_MC_CLK 2 #define TF_PM_MODE_LP1_NO_MC_CLK 2
#define TF_PM_MODE_LP2 3 #define TF_PM_MODE_LP2 3
#define TF_PM_MODE_LP2_NOFLUSH_L2 4 #define TF_PM_MODE_LP2_NOFLUSH_L2 4
#define TF_PM_MODE_NONE 5
struct trusted_foundations_platform_data { struct trusted_foundations_platform_data {
unsigned int version_major; unsigned int version_major;
......
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