1. 13 Nov, 2023 13 commits
  2. 08 Nov, 2023 1 commit
  3. 31 Oct, 2023 11 commits
    • Paolo Bonzini's avatar
      Merge tag 'kvmarm-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD · 45b890f7
      Paolo Bonzini authored
      KVM/arm64 updates for 6.7
      
       - Generalized infrastructure for 'writable' ID registers, effectively
         allowing userspace to opt-out of certain vCPU features for its guest
      
       - Optimization for vSGI injection, opportunistically compressing MPIDR
         to vCPU mapping into a table
      
       - Improvements to KVM's PMU emulation, allowing userspace to select
         the number of PMCs available to a VM
      
       - Guest support for memory operation instructions (FEAT_MOPS)
      
       - Cleanups to handling feature flags in KVM_ARM_VCPU_INIT, squashing
         bugs and getting rid of useless code
      
       - Changes to the way the SMCCC filter is constructed, avoiding wasted
         memory allocations when not in use
      
       - Load the stage-2 MMU context at vcpu_load() for VHE systems, reducing
         the overhead of errata mitigations
      
       - Miscellaneous kernel and selftest fixes
      45b890f7
    • Paolo Bonzini's avatar
      Merge tag 'kvm-x86-svm-6.7' of https://github.com/kvm-x86/linux into HEAD · be479419
      Paolo Bonzini authored
      KVM SVM changes for 6.7:
      
       - Report KVM_EXIT_SHUTDOWN instead of EINVAL if KVM intercepts SHUTDOWN while
         running an SEV-ES guest.
      
       - Clean up handling "failures" when KVM detects it can't emulate the "skip"
         action for an instruction that has already been partially emulated.  Drop a
         hack in the SVM code that was fudging around the emulator code not giving
         SVM enough information to do the right thing.
      be479419
    • Paolo Bonzini's avatar
      Merge tag 'kvm-x86-pmu-6.7' of https://github.com/kvm-x86/linux into HEAD · d5cde2e0
      Paolo Bonzini authored
      KVM PMU change for 6.7:
      
       - Handle NMI/SMI requests after PMU/PMI requests so that a PMI=>NMI doesn't
         require redoing the entire run loop due to the NMI not being detected until
         the final kvm_vcpu_exit_request() check before entering the guest.
      d5cde2e0
    • Paolo Bonzini's avatar
      Merge tag 'kvm-x86-xen-6.7' of https://github.com/kvm-x86/linux into HEAD · e122d7a1
      Paolo Bonzini authored
      KVM x86 Xen changes for 6.7:
      
       - Omit "struct kvm_vcpu_xen" entirely when CONFIG_KVM_XEN=n.
      
       - Use the fast path directly from the timer callback when delivering Xen timer
         events.  Avoid the problematic races with using the fast path by ensuring
         the hrtimer isn't running when (re)starting the timer or saving the timer
         information (for userspace).
      
       - Follow the lead of upstream Xen and ignore the VCPU_SSHOTTMR_future flag.
      e122d7a1
    • Paolo Bonzini's avatar
      Merge tag 'kvm-x86-mmu-6.7' of https://github.com/kvm-x86/linux into HEAD · f0f59d06
      Paolo Bonzini authored
      KVM x86 MMU changes for 6.7:
      
       - Clean up code that deals with honoring guest MTRRs when the VM has
         non-coherent DMA and host MTRRs are ignored, i.e. EPT is enabled.
      
       - Zap EPT entries when non-coherent DMA assignment stops/start to prevent
         using stale entries with the wrong memtype.
      
       - Don't ignore guest PAT for CR0.CD=1 && KVM_X86_QUIRK_CD_NW_CLEARED=y, as
         there's zero reason to ignore guest PAT if the effective MTRR memtype is WB.
         This will also allow for future optimizations of handling guest MTRR updates
         for VMs with non-coherent DMA and the quirk enabled.
      
       - Harden the fast page fault path to guard against encountering an invalid
         root when walking SPTEs.
      f0f59d06
    • Paolo Bonzini's avatar
      Merge tag 'kvm-x86-misc-6.7' of https://github.com/kvm-x86/linux into HEAD · f292dc8a
      Paolo Bonzini authored
      KVM x86 misc changes for 6.7:
      
       - Add CONFIG_KVM_MAX_NR_VCPUS to allow supporting up to 4096 vCPUs without
         forcing more common use cases to eat the extra memory overhead.
      
       - Add IBPB and SBPB virtualization support.
      
       - Fix a bug where restoring a vCPU snapshot that was taken within 1 second of
         creating the original vCPU would cause KVM to try to synchronize the vCPU's
         TSC and thus clobber the correct TSC being set by userspace.
      
       - Compute guest wall clock using a single TSC read to avoid generating an
         inaccurate time, e.g. if the vCPU is preempted between multiple TSC reads.
      
       - "Virtualize" HWCR.TscFreqSel to make Linux guests happy, which complain
          about a "Firmware Bug" if the bit isn't set for select F/M/S combos.
      
       - Don't apply side effects to Hyper-V's synthetic timer on writes from
         userspace to fix an issue where the auto-enable behavior can trigger
         spurious interrupts, i.e. do auto-enabling only for guest writes.
      
       - Remove an unnecessary kick of all vCPUs when synchronizing the dirty log
         without PML enabled.
      
       - Advertise "support" for non-serializing FS/GS base MSR writes as appropriate.
      
       - Use octal notation for file permissions through KVM x86.
      
       - Fix a handful of typo fixes and warts.
      f292dc8a
    • Paolo Bonzini's avatar
      Merge tag 'kvm-x86-docs-6.7' of https://github.com/kvm-x86/linux into HEAD · fadaf574
      Paolo Bonzini authored
      KVM x86 Documentation updates for 6.7:
      
       - Fix various typos, notably a confusing reference to the non-existent
         "struct kvm_vcpu_event" (the actual structure is kvm_vcpu_events, plural).
      
       - Update x86's kvm_mmu_page documentation to bring it closer to the code
         (this raced with the removal of async zapping and so the documentation is
         already stale; my bad).
      
       - Document the behavior of x86 PMU filters on fixed counters.
      fadaf574
    • Paolo Bonzini's avatar
      Merge tag 'kvm-x86-apic-6.7' of https://github.com/kvm-x86/linux into HEAD · f2336467
      Paolo Bonzini authored
      KVM x86 APIC changes for 6.7:
      
       - Purge VMX's posted interrupt descriptor *before* loading APIC state when
         handling KVM_SET_LAPIC.  Purging the PID after loading APIC state results in
         lost APIC timer IRQs as the APIC timer can be armed as part of loading APIC
         state, i.e. can immediately pend an IRQ if the expiry is in the past.
      
       - Clear the ICR.BUSY bit when handling trap-like x2APIC writes.  This avoids a
         WARN, due to KVM expecting the BUSY bit to be cleared when sending IPIs.
      f2336467
    • Paolo Bonzini's avatar
      Merge tag 'kvm-s390-next-6.7-1' of... · 140139c5
      Paolo Bonzini authored
      Merge tag 'kvm-s390-next-6.7-1' of https://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEAD
      
      - nested page table management performance counters
      140139c5
    • Paolo Bonzini's avatar
      Merge tag 'kvm-riscv-6.7-1' of https://github.com/kvm-riscv/linux into HEAD · 957eedc7
      Paolo Bonzini authored
      KVM/riscv changes for 6.7
      
      - Smstateen and Zicond support for Guest/VM
      - Virtualized senvcfg CSR for Guest/VM
      - Added Smstateen registers to the get-reg-list selftests
      - Added Zicond to the get-reg-list selftests
      - Virtualized SBI debug console (DBCN) for Guest/VM
      - Added SBI debug console (DBCN) to the get-reg-list selftests
      957eedc7
    • Paolo Bonzini's avatar
      Merge tag 'loongarch-kvm-6.7' of... · ef12ea62
      Paolo Bonzini authored
      Merge tag 'loongarch-kvm-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson into HEAD
      
      LoongArch KVM changes for v6.7
      
      Add LoongArch's KVM support. Loongson 3A5000/3A6000 supports hardware
      assisted virtualization. With cpu virtualization, there are separate
      hw-supported user mode and kernel mode in guest mode. With memory
      virtualization, there are two-level hw mmu table for guest mode and host
      mode. Also there is separate hw cpu timer with consant frequency in
      guest mode, so that vm can migrate between hosts with different freq.
      Currently, we are able to boot LoongArch Linux Guests.
      
      Few key aspects of KVM LoongArch added by this series are:
      1. Enable kvm hardware function when kvm module is loaded.
      2. Implement VM and vcpu related ioctl interface such as vcpu create,
         vcpu run etc. GET_ONE_REG/SET_ONE_REG ioctl commands are use to
         get general registers one by one.
      3. Hardware access about MMU, timer and csr are emulated in kernel.
      4. Hardwares such as mmio and iocsr device are emulated in user space
         such as IPI, irqchips, pci devices etc.
      ef12ea62
  4. 30 Oct, 2023 15 commits
    • Oliver Upton's avatar
      Merge branch kvm-arm64/pmu_pmcr_n into kvmarm/next · 123f42f0
      Oliver Upton authored
      * kvm-arm64/pmu_pmcr_n:
        : User-defined PMC limit, courtesy Raghavendra Rao Ananta
        :
        : Certain VMMs may want to reserve some PMCs for host use while running a
        : KVM guest. This was a bit difficult before, as KVM advertised all
        : supported counters to the guest. Userspace can now limit the number of
        : advertised PMCs by writing to PMCR_EL0.N, as KVM's sysreg and PMU
        : emulation enforce the specified limit for handling guest accesses.
        KVM: selftests: aarch64: vPMU test for validating user accesses
        KVM: selftests: aarch64: vPMU register test for unimplemented counters
        KVM: selftests: aarch64: vPMU register test for implemented counters
        KVM: selftests: aarch64: Introduce vpmu_counter_access test
        tools: Import arm_pmuv3.h
        KVM: arm64: PMU: Allow userspace to limit PMCR_EL0.N for the guest
        KVM: arm64: Sanitize PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR} before first run
        KVM: arm64: Add {get,set}_user for PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR}
        KVM: arm64: PMU: Set PMCR_EL0.N for vCPU based on the associated PMU
        KVM: arm64: PMU: Add a helper to read a vCPU's PMCR_EL0
        KVM: arm64: Select default PMU in KVM_ARM_VCPU_INIT handler
        KVM: arm64: PMU: Introduce helpers to set the guest's PMU
      Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      123f42f0
    • Oliver Upton's avatar
      Merge branch kvm-arm64/mops into kvmarm/next · 53ce49ea
      Oliver Upton authored
      * kvm-arm64/mops:
        : KVM support for MOPS, courtesy of Kristina Martsenko
        :
        : MOPS adds new instructions for accelerating memcpy(), memset(), and
        : memmove() operations in hardware. This series brings virtualization
        : support for KVM guests, and allows VMs to run on asymmetrict systems
        : that may have different MOPS implementations.
        KVM: arm64: Expose MOPS instructions to guests
        KVM: arm64: Add handler for MOPS exceptions
      Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      53ce49ea
    • Oliver Upton's avatar
      Merge branch kvm-arm64/writable-id-regs into kvmarm/next · a87a3643
      Oliver Upton authored
      * kvm-arm64/writable-id-regs:
        : Writable ID registers, courtesy of Jing Zhang
        :
        : This series significantly expands the architectural feature set that
        : userspace can manipulate via the ID registers. A new ioctl is defined
        : that makes the mutable fields in the ID registers discoverable to
        : userspace.
        KVM: selftests: Avoid using forced target for generating arm64 headers
        tools headers arm64: Fix references to top srcdir in Makefile
        KVM: arm64: selftests: Test for setting ID register from usersapce
        tools headers arm64: Update sysreg.h with kernel sources
        KVM: selftests: Generate sysreg-defs.h and add to include path
        perf build: Generate arm64's sysreg-defs.h and add to include path
        tools: arm64: Add a Makefile for generating sysreg-defs.h
        KVM: arm64: Document vCPU feature selection UAPIs
        KVM: arm64: Allow userspace to change ID_AA64ZFR0_EL1
        KVM: arm64: Allow userspace to change ID_AA64PFR0_EL1
        KVM: arm64: Allow userspace to change ID_AA64MMFR{0-2}_EL1
        KVM: arm64: Allow userspace to change ID_AA64ISAR{0-2}_EL1
        KVM: arm64: Bump up the default KVM sanitised debug version to v8p8
        KVM: arm64: Reject attempts to set invalid debug arch version
        KVM: arm64: Advertise selected DebugVer in DBGDIDR.Version
        KVM: arm64: Use guest ID register values for the sake of emulation
        KVM: arm64: Document KVM_ARM_GET_REG_WRITABLE_MASKS
        KVM: arm64: Allow userspace to get the writable masks for feature ID registers
      Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      a87a3643
    • Oliver Upton's avatar
      KVM: selftests: Avoid using forced target for generating arm64 headers · 70c7b704
      Oliver Upton authored
      The 'prepare' target that generates the arm64 sysreg headers had no
      prerequisites, so it wound up forcing a rebuild of all KVM selftests
      each invocation. Add a rule for the generated headers and just have
      dependents use that for a prerequisite.
      Reported-by: default avatarNina Schoetterl-Glausch <nsg@linux.ibm.com>
      Fixes: 9697d84c ("KVM: selftests: Generate sysreg-defs.h and add to include path")
      Tested-by: default avatarNina Schoetterl-Glausch <nsg@linux.ibm.com>
      Link: https://lore.kernel.org/r/20231027005439.3142015-3-oliver.upton@linux.devSigned-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      70c7b704
    • Oliver Upton's avatar
      tools headers arm64: Fix references to top srcdir in Makefile · fbb075c1
      Oliver Upton authored
      Aishwarya reports that KVM selftests for arm64 fail with the following
      error:
      
       | make[4]: Entering directory '/tmp/kci/linux/tools/testing/selftests/kvm'
       | Makefile:270: warning: overriding recipe for target
       | '/tmp/kci/linux/build/kselftest/kvm/get-reg-list'
       | Makefile:265: warning: ignoring old recipe for target
       | '/tmp/kci/linux/build/kselftest/kvm/get-reg-list'
       | make -C ../../../../tools/arch/arm64/tools/
       | make[5]: Entering directory '/tmp/kci/linux/tools/arch/arm64/tools'
       | Makefile:10: ../tools/scripts/Makefile.include: No such file or directory
       | make[5]: *** No rule to make target '../tools/scripts/Makefile.include'.
       |  Stop.
      
      It would appear that this only affects builds from the top-level
      Makefile (e.g. make kselftest-all), as $(srctree) is set to ".". Work
      around the issue by shadowing the kselftest naming scheme for the source
      tree variable.
      Reported-by: default avatarAishwarya TCV <aishwarya.tcv@arm.com>
      Fixes: 0359c946 ("tools headers arm64: Update sysreg.h with kernel sources")
      Link: https://lore.kernel.org/r/20231027005439.3142015-2-oliver.upton@linux.devSigned-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      fbb075c1
    • Oliver Upton's avatar
      Merge branch kvm-arm64/sgi-injection into kvmarm/next · 54b44ad2
      Oliver Upton authored
      * kvm-arm64/sgi-injection:
        : vSGI injection improvements + fixes, courtesy Marc Zyngier
        :
        : Avoid linearly searching for vSGI targets using a compressed MPIDR to
        : index a cache. While at it, fix some egregious bugs in KVM's mishandling
        : of vcpuid (user-controlled value) and vcpu_idx.
        KVM: arm64: Clarify the ordering requirements for vcpu/RD creation
        KVM: arm64: vgic-v3: Optimize affinity-based SGI injection
        KVM: arm64: Fast-track kvm_mpidr_to_vcpu() when mpidr_data is available
        KVM: arm64: Build MPIDR to vcpu index cache at runtime
        KVM: arm64: Simplify kvm_vcpu_get_mpidr_aff()
        KVM: arm64: Use vcpu_idx for invalidation tracking
        KVM: arm64: vgic: Use vcpu_idx for the debug information
        KVM: arm64: vgic-v2: Use cpuid from userspace as vcpu_id
        KVM: arm64: vgic-v3: Refactor GICv3 SGI generation
        KVM: arm64: vgic-its: Treat the collection target address as a vcpu_id
        KVM: arm64: vgic: Make kvm_vgic_inject_irq() take a vcpu pointer
      Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      54b44ad2
    • Oliver Upton's avatar
      Merge branch kvm-arm64/stage2-vhe-load into kvmarm/next · df26b779
      Oliver Upton authored
      * kvm-arm64/stage2-vhe-load:
        : Setup stage-2 MMU from vcpu_load() for VHE
        :
        : Unlike nVHE, there is no need to switch the stage-2 MMU around on guest
        : entry/exit in VHE mode as the host is running at EL2. Despite this KVM
        : reloads the stage-2 on every guest entry, which is needless.
        :
        : This series moves the setup of the stage-2 MMU context to vcpu_load()
        : when running in VHE mode. This is likely to be a win across the board,
        : but also allows us to remove an ISB on the guest entry path for systems
        : with one of the speculative AT errata.
        KVM: arm64: Move VTCR_EL2 into struct s2_mmu
        KVM: arm64: Load the stage-2 MMU context in kvm_vcpu_load_vhe()
        KVM: arm64: Rename helpers for VHE vCPU load/put
        KVM: arm64: Reload stage-2 for VMID change on VHE
        KVM: arm64: Restore the stage-2 context in VHE's __tlb_switch_to_host()
        KVM: arm64: Don't zero VTTBR in __tlb_switch_to_host()
      Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      df26b779
    • Oliver Upton's avatar
      Merge branch kvm-arm64/nv-trap-fixes into kvmarm/next · 51e60796
      Oliver Upton authored
      * kvm-arm64/nv-trap-fixes:
        : NV trap forwarding fixes, courtesy Miguel Luis and Marc Zyngier
        :
        :  - Explicitly define the effects of HCR_EL2.NV on EL2 sysregs in the
        :    NV trap encoding
        :
        :  - Make EL2 registers that access AArch32 guest state UNDEF or RAZ/WI
        :    where appropriate for NV guests
        KVM: arm64: Handle AArch32 SPSR_{irq,abt,und,fiq} as RAZ/WI
        KVM: arm64: Do not let a L1 hypervisor access the *32_EL2 sysregs
        KVM: arm64: Refine _EL2 system register list that require trap reinjection
        arm64: Add missing _EL2 encodings
        arm64: Add missing _EL12 encodings
      Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      51e60796
    • Oliver Upton's avatar
      Merge branch kvm-arm64/smccc-filter-cleanups into kvmarm/next · 25a35c1a
      Oliver Upton authored
      * kvm-arm64/smccc-filter-cleanups:
        : Cleanup the management of KVM's SMCCC maple tree
        :
        : Avoid the cost of maintaining the SMCCC filter maple tree if userspace
        : hasn't writen a rule to the filter. While at it, rip out the now
        : unnecessary VM flag to indicate whether or not the SMCCC filter was
        : configured.
        KVM: arm64: Use mtree_empty() to determine if SMCCC filter configured
        KVM: arm64: Only insert reserved ranges when SMCCC filter is used
        KVM: arm64: Add a predicate for testing if SMCCC filter is configured
      Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      25a35c1a
    • Oliver Upton's avatar
      Merge branch kvm-arm64/pmevtyper-filter into kvmarm/next · 7ff7dfe9
      Oliver Upton authored
      * kvm-arm64/pmevtyper-filter:
        : Fixes to KVM's handling of the PMUv3 exception level filtering bits
        :
        :  - NSH (count at EL2) and M (count at EL3) should be stateful when the
        :    respective EL is advertised in the ID registers but have no effect on
        :    event counting.
        :
        :  - NSU and NSK modify the event filtering of EL0 and EL1, respectively.
        :    Though the kernel may not use these bits, other KVM guests might.
        :    Implement these bits exactly as written in the pseudocode if EL3 is
        :    advertised.
        KVM: arm64: Add PMU event filter bits required if EL3 is implemented
        KVM: arm64: Make PMEVTYPER<n>_EL0.NSH RES0 if EL2 isn't advertised
      Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      7ff7dfe9
    • Oliver Upton's avatar
      Merge branch kvm-arm64/feature-flag-refactor into kvmarm/next · d47dcb67
      Oliver Upton authored
      * kvm-arm64/feature-flag-refactor:
        : vCPU feature flag cleanup
        :
        : Clean up KVM's handling of vCPU feature flags to get rid of the
        : vCPU-scoped bitmaps and remove failure paths from kvm_reset_vcpu().
        KVM: arm64: Get rid of vCPU-scoped feature bitmap
        KVM: arm64: Remove unused return value from kvm_reset_vcpu()
        KVM: arm64: Hoist NV+SVE check into KVM_ARM_VCPU_INIT ioctl handler
        KVM: arm64: Prevent NV feature flag on systems w/o nested virt
        KVM: arm64: Hoist PAuth checks into KVM_ARM_VCPU_INIT ioctl
        KVM: arm64: Hoist SVE check into KVM_ARM_VCPU_INIT ioctl handler
        KVM: arm64: Hoist PMUv3 check into KVM_ARM_VCPU_INIT ioctl handler
        KVM: arm64: Add generic check for system-supported vCPU features
      Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      d47dcb67
    • Oliver Upton's avatar
      Merge branch kvm-arm64/misc into kvmarm/next · 054056bf
      Oliver Upton authored
      * kvm-arm64/misc:
        : Miscellaneous updates
        :
        :  - Put an upper bound on the number of I-cache invalidations by
        :    cacheline to avoid soft lockups
        :
        :  - Get rid of bogus refererence count transfer for THP mappings
        :
        :  - Do a local TLB invalidation on permission fault race
        :
        :  - Fixes for page_fault_test KVM selftest
        :
        :  - Add a tracepoint for detecting MMIO instructions unsupported by KVM
        KVM: arm64: Add tracepoint for MMIO accesses where ISV==0
        KVM: arm64: selftest: Perform ISB before reading PAR_EL1
        KVM: arm64: selftest: Add the missing .guest_prepare()
        KVM: arm64: Always invalidate TLB for stage-2 permission faults
        KVM: arm64: Do not transfer page refcount for THP adjustment
        KVM: arm64: Avoid soft lockups due to I-cache maintenance
        arm64: tlbflush: Rename MAX_TLBI_OPS
        KVM: arm64: Don't use kerneldoc comment for arm64_check_features()
      Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      054056bf
    • Oliver Upton's avatar
      KVM: arm64: Add tracepoint for MMIO accesses where ISV==0 · d11974dc
      Oliver Upton authored
      It is a pretty well known fact that KVM does not support MMIO emulation
      without valid instruction syndrome information (ESR_EL2.ISV == 0). The
      current kvm_pr_unimpl() is pretty useless, as it contains zero context
      to relate the event to a vCPU.
      
      Replace it with a precise tracepoint that dumps the relevant context
      so the user can make sense of what the guest is doing.
      Acked-by: default avatarZenghui Yu <yuzenghui@huawei.com>
      Acked-by: default avatarMarc Zyngier <maz@kernel.org>
      Link: https://lore.kernel.org/r/20231026205306.3045075-1-oliver.upton@linux.devSigned-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      d11974dc
    • Zenghui Yu's avatar
      KVM: arm64: selftest: Perform ISB before reading PAR_EL1 · 06899aa5
      Zenghui Yu authored
      It looks like a mistake to issue ISB *after* reading PAR_EL1, we should
      instead perform it between the AT instruction and the reads of PAR_EL1.
      
      As according to DDI0487J.a IJTYVP,
      
      "When an address translation instruction is executed, explicit
       synchronization is required to guarantee the result is visible to
       subsequent direct reads of PAR_EL1."
      
      Otherwise all guest_at testcases fail on my box with
      
      ==== Test Assertion Failure ====
        aarch64/page_fault_test.c:142: par & 1 == 0
        pid=1355864 tid=1355864 errno=4 - Interrupted system call
           1	0x0000000000402853: vcpu_run_loop at page_fault_test.c:681
           2	0x0000000000402cdb: run_test at page_fault_test.c:730
           3	0x0000000000403897: for_each_guest_mode at guest_modes.c:100
           4	0x00000000004019f3: for_each_test_and_guest_mode at page_fault_test.c:1105
           5	 (inlined by) main at page_fault_test.c:1131
           6	0x0000ffffb153c03b: ?? ??:0
           7	0x0000ffffb153c113: ?? ??:0
           8	0x0000000000401aaf: _start at ??:?
        0x1 != 0x0 (par & 1 != 0)
      Signed-off-by: default avatarZenghui Yu <yuzenghui@huawei.com>
      Acked-by: default avatarMarc Zyngier <maz@kernel.org>
      Link: https://lore.kernel.org/r/20231007124043.626-2-yuzenghui@huawei.comSigned-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      06899aa5
    • Zenghui Yu's avatar
      KVM: arm64: selftest: Add the missing .guest_prepare() · beaf35b4
      Zenghui Yu authored
      Running page_fault_test on a Cortex A72 fails with
      
      Test: ro_memslot_no_syndrome_guest_cas
      Testing guest mode: PA-bits:40,  VA-bits:48,  4K pages
      Testing memory backing src type: anonymous
      ==== Test Assertion Failure ====
        aarch64/page_fault_test.c:117: guest_check_lse()
        pid=1944087 tid=1944087 errno=4 - Interrupted system call
           1	0x00000000004028b3: vcpu_run_loop at page_fault_test.c:682
           2	0x0000000000402d93: run_test at page_fault_test.c:731
           3	0x0000000000403957: for_each_guest_mode at guest_modes.c:100
           4	0x00000000004019f3: for_each_test_and_guest_mode at page_fault_test.c:1108
           5	 (inlined by) main at page_fault_test.c:1134
           6	0x0000ffff868e503b: ?? ??:0
           7	0x0000ffff868e5113: ?? ??:0
           8	0x0000000000401aaf: _start at ??:?
        guest_check_lse()
      
      because we don't have a guest_prepare stage to check the presence of
      FEAT_LSE and skip the related guest_cas testing, and we end-up failing in
      GUEST_ASSERT(guest_check_lse()).
      
      Add the missing .guest_prepare() where it's indeed required.
      Signed-off-by: default avatarZenghui Yu <yuzenghui@huawei.com>
      Acked-by: default avatarMarc Zyngier <maz@kernel.org>
      Link: https://lore.kernel.org/r/20231007124043.626-1-yuzenghui@huawei.comSigned-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      beaf35b4