- 05 Jul, 2022 16 commits
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Rodrigo Siqueira authored
We want to enable Firmware Assisted Memory (FAMS) Switching, but first, we need to add the required code infrastructure in DC before allowing it in amdgpu_dm. Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alvin Lee authored
[Why] Newer DCN should use optc3 [How] Declare optc3 vmin/vmax function in header. Signed-off-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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Eric Bernstein authored
After some experimental tests, we noticed that we need to set gpuvm_max_page_table_levels to '4' to meet the hardware requirements. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Tested-by:
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Chris Park authored
[Why] For Pixel Rate control, when on HDMI, HDMI DTO should be selected instead of DP DTO. [How] Pass HDMI parameter for HDMI stream, and select correct DTO. Signed-off-by:
Chris Park <chris.park@amd.com> Tested-by:
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Alvin Lee authored
For MPO we want to allocate less than maximum DET for MPO pipes because we need enogh buffer to move DET back to other pipes when removing an MPO plane. Also update regular DET allocation to use DET override (DCN32 has an internal policy which driver does not want to use) Signed-off-by:
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Rodrigo Siqueira authored
Currently, we check if pixel_encoding is equal to PIXEL_ENCODING_YCBCR422 to get the k1/k2 div parameters. This commit changes this logic slightly by checking if two pixels per container are used. Signed-off-by:
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Samson Tam authored
[Why] Most of the time, a single display uses the ODM combine. When using multi-display, we use ODM combine only if it is necessary. These cases are not flexible enough for us, and we can improve them to take advantage of our hardware. We want to have more control over the ODM policy. [How] This commit add a new debug flag named enable_single_display_2to1_odm_policy to control the ODM policy and another flag named enable_dp_dig_pixel_rate_div_policy to fine control the ODM combine. This is possible by adding a new "pipe.dest" parameter that can be set to ODM 2:1 combined if we use a single display. For dynamic ODM combine, when using DP-DIG, DCN applies K2=2 settings for ODM combine. Note that this feature affects the following registers: - timing.pix_clk_100khz -> DP_VID_M, DP_VID_N - requested_pix_clk_100hz -> DP_DTOn_PHASE - OTGn_PIXEL_RATE_DIVK2 - DP_PIXEL_PER_CYCLE_PROCESSING_MODE - DIG_FIFO_OUTPUT_PIXEL_MODE - DP_VID_N_MUL Acked-by:
Samson Tam <Samson.Tam@amd.com> Tested-by:
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Eric Bernstein authored
Add function to set pixels per cycle in DIG stream encoder Acked-by:
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Martin Leung authored
[WHY]: Lut pipeline will be hooked up differently in some asics need to add new interfaces and missing registers. [HOW]: Add missing registers and hook up programming from DPP for pre-blend lut. Acked-by:
Martin Leung <Martin.Leung@amd.com> Tested-by:
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Alvin Lee authored
This commit enables the SubVP feature. To achieve that, we need to: - Don't force p-state disallow on SubVP (can't block dummy p-state) - Send calculated watermark to DMCUB for SubVP - Adjust CAB mode message to PMFW - Add a proper locking sequence for SubVP - Various fixes to SubVP static analysis and determining SubVP config - Currently SubVP not supported with pipe split so merge all pipes before setting up SubVp Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Alan Liu <HaoPing.Liu@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
We are missing some ACP registers/mask value for some specific ASICs. This commit includes it to those ASICs that support it. Signed-off-by:
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Stanley.Yang authored
It should not init whole ras bad page framework on sriov guest side due to it is handled on host side. Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Stanley.Yang authored
GFX is the only IP block that RAS TA needs to program the hardware when receiving enable_feature command. Changed from V1: remove amdgpu_ras_need_send_ras_feature inline function, use GFX RAS block check directly. Signed-off-by: -
Evan Quan authored
And bump the version to 0x2A. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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Lang Yu authored
We don't need to validate and map root PD specially here, it would be validated and mapped by amdgpu_vm_validate_pt_bos if it is evicted. The special case is when turning a GFX VM to a compute VM, if vm_update_mode changed, we should make sure root PD gets mapped. So just map root PD after updating vm->update_funcs in amdgpu_vm_make_compute whether the vm_update_mode changed or not. v3: - Add some comments suggested by Christian. v2: - Don't rename vm_validate_pt_pd_bos and make it public. Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Expose a new dc debug mask enum to force a subviewport memory clock switch to facilitate easy testing. Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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- 30 Jun, 2022 21 commits
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Alex Deucher authored
Properly handle FP code in dcn32_clk_mgr.c. Fixes: 265280b9 ("drm/amd/display: add CLKMGR changes for DCN32/321") Reviewed-by:
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Rodrigo Siqueira authored
When we tried to compile DCN32/321 for 32-bit architecture, we got this error message: ERROR: modpost: "__nedf2" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! This commit fixes this issue by rewriting a small part of the dcn32_build_wm_range_table. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Randy Dunlap <rdunlap@infradead.org> Fixes: 265280b9 ("drm/amd/display: add CLKMGR changes for DCN32/321") Acked-by:
Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Reviewed-by:
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Rodrigo Siqueira authored
Sometimes when trying to enable some feature, we have to define some values with educated guesses, but we mark those values as TBD, which means "To Be Determined". However, the correct way to approach it is by loading that information from the firmware. Anyway, some of the values that we were experimenting with caused this issue: ERROR: modpost: "__muldf3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! This commit fixes this issue by removing the division by two since it is harmless in this case. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Randy Dunlap <rdunlap@infradead.org> Fixes: 265280b9 ("drm/amd/display: add CLKMGR changes for DCN32/321") Acked-by:
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Rodrigo Siqueira authored
When we tried to compile DCN32/321 for 32-bit architecture, we got this error message: ERROR: modpost: "__floatunsidf" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! This was caused because we were trying to assign an unsigned int to a double value which causes issues for 32-bit architecture. This issue can be fixed by changing the value type. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Randy Dunlap <rdunlap@infradead.org> Fixes: 265280b9 ("drm/amd/display: add CLKMGR changes for DCN32/321") Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Acked-by:
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Rodrigo Siqueira authored
While we tried to build amdgpu on i386, we got this error: ERROR: modpost: "__umoddi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! This commit fixes this issue by replacing the standard module operator with div_u64_rem. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Randy Dunlap <rdunlap@infradead.org> Fixes: d3dfceb5 ("drm/amd/display: Add dependant changes for DCN32/321") Reported-by:
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Philip Yang authored
Indicate SMI profiling events available. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
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Philip Yang authored
The synchronize_rcu may take several ms, which noticeably slows down applications close SMI event handle. Use call_rcu to free client->fifo and client asynchronously and eliminate the synchronize_rcu call in the user thread. Signed-off-by:
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Philip Yang authored
SVM range unmapped from GPUs when range is unmapped from CPU, or with xnack on from MMU notifier when range is evicted or migrated. Signed-off-by:
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Philip Yang authored
Output user queue eviction and restore event. User queue eviction may be triggered by svm or userptr MMU notifier, TTM eviction, device suspend and CRIU checkpoint and restore. User queue restore may be rescheduled if eviction happens again while restore. Signed-off-by:
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Philip Yang authored
For migration start and end event, output timestamp when migration starts, ends, svm range address and size, GPU id of migration source and destination and svm range attributes, Migration trigger could be prefetch, CPU or GPU page fault and TTM eviction. Signed-off-by:
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Philip Yang authored
Use ktime_get_boottime_ns() as timestamp to correlate with other APIs. Output timestamp when GPU recoverable fault starts and ends to recover the fault, if migration happened or only GPU page table is updated to recover, fault address, if read or write fault. Signed-off-by:
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Philip Yang authored
Process receive event from same process by default. Add a flag to be able to receive event from all processes, this requires super user permission. Event using pid 0 to send the event to all processes, to keep the default behavior of existing SMI events. Signed-off-by:
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Philip Yang authored
Define new system management interface event IDs for migration, GPU recoverable page fault, user queues eviction, restore and unmap from GPU events and corresponding event triggers, those will be implemented in the following patches. Signed-off-by:
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Jack Xiao authored
This reverts commit 8748de87 since drv enabled mes to access registers. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
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Jack Xiao authored
Enable mes to access registers. v2: squash mes sched ring enablement flag Signed-off-by:
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Jack Xiao authored
Add mes register access routines: 1. read register 2. write register 3. wait register 4. write and wait register Signed-off-by:
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Jack Xiao authored
Add misc op commands in mes11. Signed-off-by:
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Jonathan Kim authored
GFX10 and up have work group processors (WGP) and WGP mode is the native compile mode. KFD and ROCr have no visibility into whether a dispatch is operating in CU or WGP mode. Enforce CU masking to be pairwise continguous in enablement and round robin distribute CUs across the SEs in a pairwise manner to assume WGP mode at all times. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
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Jack Xiao authored
Add common interface for mes misc op, including accessing register interface. Signed-off-by:
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Jack Xiao authored
Update MES firmware api for accessing registers. Signed-off-by:
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Alex Deucher authored
Fixes this issue: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:5094: warning: expecting prototype for amdgpu_device_gpu_recover_imp(). Prototype was for amdgpu_device_gpu_recover() instead Fixes: cf727044 ("drm/amdgpu: Rename amdgpu_device_gpu_recover_imp back to amdgpu_device_gpu_recover") Reviewed-by:
Kent Russell <kent.russell@amd.com> Reported-by:
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- 29 Jun, 2022 3 commits
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Chandan Vurdigere Nataraj authored
[Why] Redundant if-else cases for repeater and non-repeater checks [How] Without changing the core logic, rearranged the code by removing redundant checks Signed-off-by:
Chandan Vurdigere Nataraj <chandan.vurdigerenataraj@amd.com> Reviewed-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Some userspace expect a backwards compatible modifier on DCN32/321. For hardware with num_pipes more than 16, we expose the most efficient modifier first. As a fall back method, we need to expose slightly inefficient modifier AMD_FMT_MOD_TILE_GFX9_64K_R_X after the best option. Also set the number of packers to fixed value as required per hardware documentation. This value is cached during hardware initialization and can be read through the base driver. Signed-off-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] TA firmware is needed to enable HDCP. Changes in v2: Load separate firmware for PSP 13.0.0 Signed-off-by:
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