- 12 Mar, 2019 1 commit
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Abel Vesa authored
IMX8MQ_CLK_USB_PHY_REF changes from 163 to 153, this way removing the gap. All the following clock ids are now decreased by 10 to keep the numbering right. Doing this, the IMX8MQ_CLK_CSI2_CORE is not overlapped with IMX8MQ_CLK_GPT1 anymore. IMX8MQ_CLK_GPT1_ROOT changes from 193 to 183 and all the following ids are updated accordingly. Reported-by:
Patrick Wildt <patrick@blueri.se> Fixes: 1cf3817b ("dt-bindings: Add binding for i.MX8MQ CCM") Signed-off-by:
Abel Vesa <abel.vesa@nxp.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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- 08 Mar, 2019 11 commits
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Tony Lindgren authored
Commit a72d7850 ("clk: ti: Prepare for remove of OF node name") changed the code to use kasprintf() for provider->clkdm_name but also changed the offset used later on by three. We don't need to change the offset as we already have the extra three characters in the format for kasprintf with "%pOFnxxx". This caused the clocks with TI_CLK_CLKCTRL_COMPAT to have NULL clk->clkdm_name for omap4 and 5. And null clkdm_name can cause module reset, enable, and idle to fail. The issue can also be seen also when enabling DEBUG for clkctrl.c and then we start seeing "clock: could not associate" messages for omap4 and 5 as the generated name is something like "l4_wkclkdm" instead of "l4_wkup_clkdm" that's needed. Let's fix the issue with a partial revert of commit a72d7850 ("clk: ti: Prepare for remove of OF node name"). ALso note that in general code should not depend on the dts node names. And the node names should be generic types like clock-domain in this case. This could be fixed later by using separate compatible properties for the clockdomains, or by adding soc_device_match() table with reg offsets to the driver. But let's fix the regression first. Fixes: a72d7850 ("clk: ti: Prepare for remove of OF node name") Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Kuninori Morimoto authored
of_clk_get_by_name() is using -1 for __of_clk_get() index. It will go to of_parse_clkspec(), and be used for of_parse_phandle_with_args(). Here, if user doesn't specify clock name (= of_clk_get_by_name(np, NULL)), this index is still -1, and of_parse_phandle_with_args() will return -EINVAL (This index will be updated if if it had clock name). clk_get_by_name(np, NULL) should work, then, default index should be 0 instead of -1. This patch fixes it. Fixes: 4472287a ("clk: Introduce of_clk_get_hw_from_clkspec()") Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Stephen Boyd authored
* 'clk-parent-rewrite' (early part): clk: Move of_clk_*() APIs into clk.c from clkdev.c clk: Inform the core about consumer devices clk: Introduce of_clk_get_hw_from_clkspec() clk: core: clarify the check for runtime PM clk: Combine __clk_get() and __clk_create_clk()
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Stephen Boyd authored
- Convert a few clk bindings to JSON schema format - 3rd ECO fix for Mediatek MT2712 SoCs * clk-typo: clk: samsung: fix typo * clk-json-schema: dt-bindings: clock: Convert fixed-factor-clock to json-schema dt-bindings: clock: Convert fixed-clock binding to json-schema * clk-mtk-2712-eco: clk: mediatek: update clock driver of MT2712 dt-bindings: clock: add clock for MT2712 * clk-rockchip: clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks clk: rockchip: fix frac settings of GPLL clock for rk3328
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Stephen Boyd authored
* clk-at91: clk: at91: programmable: remove unneeded register read clk: at91: optimize clk_round_rate() for AUDIO_PLL clk: at91: enable AUDIOPLL as source for PCKx on SAMA5D2
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Stephen Boyd authored
Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk-crit' and 'clk-mtk' into clk-next * clk-ingenic: clk: ingenic: Remove set but not used variable 'enable' clk: ingenic: Fix doc of ingenic_cgu_div_info clk: ingenic: Fix round_rate misbehaving with non-integer dividers clk: ingenic: jz4740: Fix gating of UDC clock * clk-mtk-mux: clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel clk: mediatek: add MUX_GATE_FLAGS_2 * clk-qcom-sdm845-pcie: clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks * clk-mtk-crit: clk: mediatek: Mark bus and DRAM related clocks as critical clk: mediatek: Add flags to mtk_gate clk: mediatek: Add MUX_FLAGS macro * clk-mtk: clk: mediatek: correct cpu clock name for MT8173 SoC
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Stephen Boyd authored
Merge branches 'clk-qcom-msm8998', 'clk-fractional-parent', 'clk-x86-mv' and 'clk-SA-fixes' into clk-next - Updates for qcom MSM8998 GCC clks - qcom MSM8998 RPM managed clks - Random static analysis fixes for clk drivers * clk-qcom-msm8998: clk: qcom: Make common clk_hw registrations clk: qcom: smd: Add support for MSM8998 rpm clocks clk: qcom: Skip halt checks on gcc_usb3_phy_pipe_clk for 8998 clk: qcom: Add missing freq for usb30_master_clk on 8998 clk: qcom: Add CLK_SET_RATE_PARENT for 8998 branch clocks * clk-fractional-parent: clk: fractional-divider: check parent rate only if flag is set * clk-x86-mv: clk: x86: Move clk-lpss.h to platform_data/x86 * clk-SA-fixes: clk: mediatek: fix platform_no_drv_owner.cocci warnings clk: tegra: dfll: Fix debugfs_simple_attr.cocci warnings clk: qoriq: Improve an error message
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Stephen Boyd authored
Merge branches 'clk-qcom-rpmh', 'clk-gpio-sleep', 'clk-stm32mp1', 'clk-qcom-qcs404' and 'clk-actions-s500' into clk-next - IPA clk support on Qualcomm RPMh clk controllers - Support sleeping gpios in clk-gpio type - Minor fixes for STM32MP1 clk driver (parents, critical flag, etc.) - Actions Semi S500 SoC clk support * clk-qcom-rpmh: clk: qcom: clk-rpmh: Add IPA clock support * clk-gpio-sleep: clk: clk-gpio: add support for sleeping GPIOs in gpio-gate-clk * clk-stm32mp1: dt-bindings: clock: remove unused definition for stm32mp1 clk: stm32mp1: fix bit width of hse_rtc divider clk: stm32mp1: remove unnecessary CLK_DIVIDER_ALLOW_ZERO flag clk: stm32mp1: fix HSI divider flag clk: stm32mp1: fix mcu divider table clk: stm32mp1: set ck_csi as critical clock clk: stm32mp1: add CLK_SET_RATE_NO_REPARENT to Kernel clocks clk: stm32mp1: parent clocks update * clk-qcom-qcs404: clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs clk: qcom: remove empty lines in clk-rcg.h * clk-actions-s500: clk: actions: Add clock driver for S500 SoC dt-bindings: clock: Add DT bindings for Actions Semi S500 CMU clk: actions: Add configurable PLL delay
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Stephen Boyd authored
Merge branches 'clk-imx', 'clk-samsung', 'clk-ti', 'clk-uniphier-gear' and 'clk-mmp2-lcdc' into clk-next - Split LCDC into two clks on the Marvell MMP2 SoC * clk-imx: clk: imx8mq: add GPIO clocks to clock tree clk: imx: Refactor entire sccg pll clk clk: imx: scu: add cpu frequency scaling support clk: imx: imx8mm: Mark init function __init clk: imx8mq: Add the missing ARM clock dt-bindings: imx8mq-clock: Add the missing ARM clock clk: imx: imx8mq: Fix the rate propagation for arm pll clk: imx8mq: Add support for the CLKO1 clock clk: imx8mq: Fix the CLKO2 source select list clk: imx8mq: Add missing M4 clocks clk: imx: Add clock driver support for imx8mm dt-bindings: imx: Add clock binding doc for imx8mm clk: imx: Add PLLs driver for imx8mm soc clk: imx5: add imx5_SCC2_IPG_GATE clk: imx: scu: add set parent support clk: imx: scu: add fallback compatible string support clk: imx8mq: Make parent names arrays const pointers clk: imx: Make parents const pointer in mux wrappers clk: imx: Make parent_names const pointer in composite-8m * clk-samsung: clk: samsung: s3c2443: Mark expected switch fall-through clk: samsung: exynos5: Fix kfree() of const memory on setting driver_override clk: samsung: exynos5: Fix possible NULL pointer exception on platform_device_alloc() failure clk: samsung: exynos5433: Add selected IMEM clocks clk: samsung: dt-bindings: Document Exynos5433 IMEM CMU clk: samsung: exynos5433: Fix name typo in sssx clk: samsung: exynos5433: Fix definition of CLK_ACLK_IMEM_{200, 266} clocks clk: samsung: dt-bindings: Add Exynos5433 IMEM CMU clock IDs * clk-ti: clk: clk-twl6040: Fix imprecise external abort for pdmclk ARM: OMAP2+: hwmod: disable ick autoidling when a hwmod requires that clk: ti: check clock type before doing autoidle ops clk: ti: add a usecount for autoidle clk: ti: generalize the init sequence of clk_hw_omap clocks clk: ti: remove usage of CLK_IS_BASIC clk: ti: add new API for checking if a provided clock is an OMAP clock clk: ti: move clk_hw_omap list handling under generic part of the driver * clk-uniphier-gear: clk: uniphier: Fix update register for CPU-gear * clk-mmp2-lcdc: clk: mmp2: separate LCDC peripheral clk form the display clock dt-bindings: marvell,mmp2: Add clock id for the LCDC clock
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Stephen Boyd authored
Merge branches 'clk-optional', 'clk-devm-clkdev-register', 'clk-allwinner', 'clk-meson' and 'clk-renesas' into clk-next - Add a {devm_}clk_get_optional() API - Add devm_clk_hw_register_clkdev() API to manage clkdev lookups * clk-optional: clk: Add (devm_)clk_get_optional() functions clk: Add comment about __of_clk_get_by_name() error values * clk-devm-clkdev-register: clk: clk-st: avoid clkdev lookup leak at remove clk: clk-max77686: Clean clkdev lookup leak and use devm clkdev: add managed clkdev lookup registration * clk-allwinner: clk: sunxi-ng: sun8i-a23: Enable PLL-MIPI LDOs when ungating it * clk-meson: (22 commits) clk: meson: meson8b: fix the naming of the APB clocks dt-bindings: clock: meson8b: add APB clock definition clk: meson: Add G12A AO Clock + Reset Controller dt-bindings: clk: add G12A AO Clock and Reset Bindings clk: meson: factorise meson64 peripheral clock controller drivers clk: meson: g12a: add peripheral clock controller dt-bindings: clk: meson: add g12a periph clock controller bindings clk: meson: pll: update driver for the g12a clk: meson: rework and clean drivers dependencies clk: meson: axg-audio does not require syscon clk: meson: use CONFIG_ARCH_MESON to enter meson clk directory clk: export some clk_hw function symbols for module drivers clk: meson: ao-clkc: claim clock controller input clocks from DT clk: meson: axg: claim clock controller input clock from DT clk: meson: gxbb: claim clock controller input clock from DT clk: meson: meson8b: add the GPU clock tree clk: meson: meson8b: use a separate clock table for Meson8 clk: meson: axg-ao: add 32k generation subtree clk: meson: gxbb-ao: replace cec-32k with the dual divider clk: meson: add dual divider clock driver ... * clk-renesas: clk: renesas: r8a774a1: Fix LAST_DT_CORE_CLK clk: renesas: r8a774c0: Fix LAST_DT_CORE_CLK clk: renesas: r8a774c0: Add TMU clock clk: renesas: r8a77980: Add RPC clocks clk: renesas: rcar-gen3: Add RPC clocks clk: renesas: rcar-gen3: Add spinlock clk: renesas: rcar-gen3: Factor out cpg_reg_modify() clk: renesas: r8a774c0: Correct parent clock of DU clk: renesas: r8a774a1: Add missing CANFD clock clk: renesas: r8a774c0: Add missing CANFD clock
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Stephen Boyd authored
Merge branches 'clk-of-refcount', 'clk-mmio-fixed-clock', 'clk-remove-clps', 'clk-socfpga-parent' and 'clk-struct-size' into clk-next - Various DT of_node refcount fixes - Support for fixed rate clks populated from an MMIO register - Remove clps711x driver as the board support is gone * clk-of-refcount: clk: dove: fix refcount leak in dove_clk_init() clk: mv98dx3236: fix refcount leak in mv98dx3236_clk_init() clk: armada-xp: fix refcount leak in axp_clk_init() clk: kirkwood: fix refcount leak in kirkwood_clk_init() clk: armada-370: fix refcount leak in a370_clk_init() clk: vf610: fix refcount leak in vf610_clocks_init() clk: imx7d: fix refcount leak in imx7d_clocks_init() clk: imx6sx: fix refcount leak in imx6sx_clocks_init() clk: imx6q: fix refcount leak in imx6q_clocks_init() clk: samsung: exynos4: fix refcount leak in exynos4_get_xom() clk: socfpga: fix refcount leak clk: ti: fix refcount leak in ti_dt_clocks_register() clk: qoriq: fix refcount leak in clockgen_init() clk: highbank: fix refcount leak in hb_clk_init() * clk-mmio-fixed-clock: clk: Add Fixed MMIO clock driver dt-bindings: clk: Add bindings for Fixed MMIO clock * clk-remove-clps: clk: clps711x: Remove board support * clk-socfpga-parent: clk: socfpga: Don't have get_parent for single parent ops * clk-struct-size: clk: imx: imx7ulp: use struct_size() in kzalloc()
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- 01 Mar, 2019 5 commits
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Stephen Boyd authored
The API between clk.c and clkdev.c is purely getting the clk_hw structure (or the struct clk if it's not CCF) and then turning that struct clk_hw pointer into a struct clk pointer via clk_hw_create_clk(). There's no need to complicate clkdev.c with these DT parsing details that are only relevant to the common clk framework. Move the DT parsing logic into the core framework and just expose the APIs to get a clk_hw pointer and convert it. Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Jerome Brunet <jbrunet@baylibre.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Jeffrey Hugo <jhugo@codeaurora.org> Cc: Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Stephen Boyd authored
We'd like to have a pointer to the device that's consuming a particular clk in the clk framework so we can link the consumer to the clk provider with a PM device link. Add a device argument to clk_hw_create_clk() for this so it can be used in subsequent patches to add and remove the link. Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Jerome Brunet <jbrunet@baylibre.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Jeffrey Hugo <jhugo@codeaurora.org> Cc: Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Stephen Boyd authored
We want to get struct clk_hw pointers from a DT clk specifier (i.e. a clocks property) so that we can find parent clks without searching for globally unique clk names. This should save time by avoiding the global string search for clks that are external to the clock controller providing the clk and let us move away from string comparisons in general. Introduce of_clk_get_hw_from_clkspec() which is largely the DT parsing part of finding clks implemented in clkdev.c and have that return a clk_hw pointer instead of converting that into a clk pointer. This lets us push up the clk pointer creation to the caller in clk_get() and avoids the need to push the dev_id and con_id throughout the DT parsing code. Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Jerome Brunet <jbrunet@baylibre.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Jeffrey Hugo <jhugo@codeaurora.org> Cc: Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Miquel Raynal authored
Currently, the core->dev entry is populated only if runtime PM is enabled. Doing so prevents accessing the device structure in any case. Keep the same logic but instead of using the presence of core->dev as the only condition, also check the status of pm_runtime_enabled(). Then, we can set the core->dev pointer at any time as long as a device structure is available. This change will help supporting device links in the clock subsystem. Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Cc: Jerome Brunet <jbrunet@baylibre.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Jeffrey Hugo <jhugo@codeaurora.org> Cc: Chen-Yu Tsai <wens@csie.org> [sboyd@kernel.org: Change to a boolean flag] Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Stephen Boyd authored
The __clk_get() function is practically a private clk implementation detail now. No architecture defines it, and given that new code should be using the common clk framework there isn't a need for it to keep existing just to serve clkdev purposes. Let's fold it into the __clk_create_clk() function and make that a little more generic by renaming it to clk_hw_create_clk(). This will allow the framework to create a struct clk handle to a particular clk_hw pointer and link it up as a consumer wherever that's needed. Doing this also lets us get rid of the __clk_free_clk() API that had to be kept in sync with __clk_put(). Splitting that API up into the "link and unlink from consumer list" phase and "free the clk pointer" phase allows us to reuse that logic in a couple places, simplifying the code. Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Jerome Brunet <jbrunet@baylibre.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Jeffrey Hugo <jhugo@codeaurora.org> Cc: Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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- 28 Feb, 2019 1 commit
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Anson Huang authored
i.MX8MQ has clock gate for each GPIO bank, add them into clock tree for GPIO driver to manage. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Reviewed-by:
Fabio Estevam <festevam@gmail.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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- 26 Feb, 2019 8 commits
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Seiya Wang authored
Correct cpu clock name from ca57 to ca72 since MT8173 does use cortex-a72. Signed-off-by:
Seiya Wang <seiya.wang@mediatek.com> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Abel Vesa authored
Make the entire combination of plls to be one single clock. The parents used for bypasses are specified each as an index in the parents list. The determine_rate does a lookup throughout all the possible combinations for all the divs and returns the best possible 'setup' which in turn is used by set_rate later to set up all the divs and bypasses. Signed-off-by:
Abel Vesa <abel.vesa@nxp.com> Tested-by:
Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Anson Huang authored
On NXP's i.MX SoCs with system controller inside, CPU frequency scaling can ONLY be done by system controller firmware, and it can ONLY be requested from secure mode, so Linux kernel has to call ARM SMC to trap to ARM-Trusted-Firmware to request system controller firmware to do CPU frequency scaling. This patch adds i.MX system controller CPU frequency scaling support, it reuses cpufreq-dt driver and implement the CPU frequency scaling inside SCU clock driver. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Jasper Mattsson authored
Currently, DRAM-related clocks are not marked with CLK_IS_CRITICAL for MT6797. This causes memory corruption when the system is booted without clk_ignore_unused. This patch marks MUX ddrphycfg_sel as well as gates infra_dramc_f26m and infra_dramc_b_f26m as CLK_IS_CRITICAL. Signed-off-by:
Jasper Mattsson <jasu@njomotys.info> Signed-off-by:
Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Jasper Mattsson authored
This is required to mark gates as CLK_IS_CRITICAL. Signed-off-by:
Jasper Mattsson <jasu@njomotys.info> Acked-by:
Mars Cheng <mars.cheng@mediatek.com> Signed-off-by:
Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Jasper Mattsson authored
This is required to mark outputs of certain MUXes as CLK_IS_CRITICAL. Signed-off-by:
Jasper Mattsson <jasu@njomotys.info> Acked-by:
Mars Cheng <mars.cheng@mediatek.com> Signed-off-by:
Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Bjorn Andersson authored
The PCIe PIPE clock in the GCC is fed by the PIPE clock coming from the PHY, describe this relationship. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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YueHaibing authored
Fixes gcc '-Wunused-but-set-variable' warning: drivers/clk/ingenic/cgu.c: In function 'ingenic_pll_recalc_rate': drivers/clk/ingenic/cgu.c:86:15: warning: variable 'enable' set but not used [-Wunused-but-set-variable] It's not used after commit ab27eb4b ("clk: ingenic: Add code to enable/disable PLLs") Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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- 25 Feb, 2019 5 commits
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Nicolas Ferre authored
This register read is a leftover of a previous read/modify/write. We now use regmap_update_bits(), so we don't need it anymore. Signed-off-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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chunhui dai authored
The MUX clock of dpi1_sel should select the closet clock for itself. We could add this flag to enable this function of MUX in CCF. Signed-off-by:
chunhui dai <chunhui.dai@mediatek.com> Signed-off-by:
wangyan wang <wangyan.wang@mediatek.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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chunhui dai authored
Add MUX_GATE_FLAGS_2 for the clock which needs to set two falgs. Such as some mux need to set the flags of "CLK_MUX_ROUND_CLOSEST". Signed-off-by:
chunhui dai <chunhui.dai@mediatek.com> Signed-off-by:
wangyan wang <wangyan.wang@mediatek.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Fabrizio Castro authored
Enum LAST_DT_CORE_CLK needs updating as R8A774A1_CLK_CANFD was recently added and it's the core clock with the highest index. Signed-off-by:
Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by:
Chris Paterson <chris.paterson2@renesas.com> Fixes: 9d034e15 ("clk: renesas: r8a774a1: Add missing CANFD clock") Reviewed-by:
Simon Horman <horms+renesas@verge.net.au> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Linus Torvalds authored
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- 24 Feb, 2019 8 commits
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git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds authored
Pull KVM fixes from Paolo Bonzini: "Bug fixes" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: MMU: record maximum physical address width in kvm_mmu_extended_role kvm: x86: Return LA57 feature based on hardware capability x86/kvm/mmu: fix switch between root and guest MMUs s390: vsie: Use effective CRYCBD.31 to check CRYCBD validity
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git://git.kernel.org/pub/scm/linux/kernel/git/davem/netLinus Torvalds authored
Pull networking fixes from David Miller: "Hopefully the last pull request for this release. Fingers crossed: 1) Only refcount ESP stats on full sockets, from Martin Willi. 2) Missing barriers in AF_UNIX, from Al Viro. 3) RCU protection fixes in ipv6 route code, from Paolo Abeni. 4) Avoid false positives in untrusted GSO validation, from Willem de Bruijn. 5) Forwarded mesh packets in mac80211 need more tailroom allocated, from Felix Fietkau. 6) Use operstate consistently for linkup in team driver, from George Wilkie. 7) ThunderX bug fixes from Vadim Lomovtsev. Mostly races between VF and PF code paths. 8) Purge ipv6 exceptions during netdevice removal, from Paolo Abeni. 9) nfp eBPF code gen fixes from Jiong Wang. 10) bnxt_en firmware timeout fix from Michael Chan. 11) Use after free in udp/udpv6 error handlers, from Paolo Abeni. 12) Fix a race in x25_bind triggerable by syzbot, from Eric Dumazet" * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (65 commits) net: phy: realtek: Dummy IRQ calls for RTL8366RB tcp: repaired skbs must init their tso_segs net/x25: fix a race in x25_bind() net: dsa: Remove documentation for port_fdb_prepare Revert "bridge: do not add port to router list when receives query with source 0.0.0.0" selftests: fib_tests: sleep after changing carrier. again. net: set static variable an initial value in atl2_probe() net: phy: marvell10g: Fix Multi-G advertisement to only advertise 10G bpf, doc: add bpf list as secondary entry to maintainers file udp: fix possible user after free in error handler udpv6: fix possible user after free in error handler fou6: fix proto error handler argument type udpv6: add the required annotation to mib type mdio_bus: Fix use-after-free on device_register fails net: Set rtm_table to RT_TABLE_COMPAT for ipv6 for tables > 255 bnxt_en: Wait longer for the firmware message response to complete. bnxt_en: Fix typo in firmware message timeout logic. nfp: bpf: fix ALU32 high bits clearance bug nfp: bpf: fix code-gen bug on BPF_ALU | BPF_XOR | BPF_K Documentation: networking: switchdev: Update port parent ID section ...
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Linus Walleij authored
This fixes a regression introduced by commit 0d2e778e "net: phy: replace PHY_HAS_INTERRUPT with a check for config_intr and ack_interrupt". This assumes that a PHY cannot trigger interrupt unless it has .config_intr() or .ack_interrupt() implemented. A later patch makes the code assume both need to be implemented for interrupts to be present. But this PHY (which is inside a DSA) will happily fire interrupts without either callback. Implement dummy callbacks for .config_intr() and .ack_interrupt() in the phy header to fix this. Tested on the RTL8366RB on D-Link DIR-685. Fixes: 0d2e778e ("net: phy: replace PHY_HAS_INTERRUPT with a check for config_intr and ack_interrupt") Cc: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Eric Dumazet authored
syzbot reported a WARN_ON(!tcp_skb_pcount(skb)) in tcp_send_loss_probe() [1] This was caused by TCP_REPAIR sent skbs that inadvertenly were missing a call to tcp_init_tso_segs() [1] WARNING: CPU: 1 PID: 0 at net/ipv4/tcp_output.c:2534 tcp_send_loss_probe+0x771/0x8a0 net/ipv4/tcp_output.c:2534 Kernel panic - not syncing: panic_on_warn set ... CPU: 1 PID: 0 Comm: swapper/1 Not tainted 5.0.0-rc7+ #77 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 Call Trace: <IRQ> __dump_stack lib/dump_stack.c:77 [inline] dump_stack+0x172/0x1f0 lib/dump_stack.c:113 panic+0x2cb/0x65c kernel/panic.c:214 __warn.cold+0x20/0x45 kernel/panic.c:571 report_bug+0x263/0x2b0 lib/bug.c:186 fixup_bug arch/x86/kernel/traps.c:178 [inline] fixup_bug arch/x86/kernel/traps.c:173 [inline] do_error_trap+0x11b/0x200 arch/x86/kernel/traps.c:271 do_invalid_op+0x37/0x50 arch/x86/kernel/traps.c:290 invalid_op+0x14/0x20 arch/x86/entry/entry_64.S:973 RIP: 0010:tcp_send_loss_probe+0x771/0x8a0 net/ipv4/tcp_output.c:2534 Code: 88 fc ff ff 4c 89 ef e8 ed 75 c8 fb e9 c8 fc ff ff e8 43 76 c8 fb e9 63 fd ff ff e8 d9 75 c8 fb e9 94 f9 ff ff e8 bf 03 91 fb <0f> 0b e9 7d fa ff ff e8 b3 03 91 fb 0f b6 1d 37 43 7a 03 31 ff 89 RSP: 0018:ffff8880ae907c60 EFLAGS: 00010206 RAX: ffff8880a989c340 RBX: 0000000000000000 RCX: ffffffff85dedbdb RDX: 0000000000000100 RSI: ffffffff85dee0b1 RDI: 0000000000000005 RBP: ffff8880ae907c90 R08: ffff8880a989c340 R09: ffffed10147d1ae1 R10: ffffed10147d1ae0 R11: ffff8880a3e8d703 R12: ffff888091b90040 R13: ffff8880a3e8d540 R14: 0000000000008000 R15: ffff888091b90860 tcp_write_timer_handler+0x5c0/0x8a0 net/ipv4/tcp_timer.c:583 tcp_write_timer+0x10e/0x1d0 net/ipv4/tcp_timer.c:607 call_timer_fn+0x190/0x720 kernel/time/timer.c:1325 expire_timers kernel/time/timer.c:1362 [inline] __run_timers kernel/time/timer.c:1681 [inline] __run_timers kernel/time/timer.c:1649 [inline] run_timer_softirq+0x652/0x1700 kernel/time/timer.c:1694 __do_softirq+0x266/0x95a kernel/softirq.c:292 invoke_softirq kernel/softirq.c:373 [inline] irq_exit+0x180/0x1d0 kernel/softirq.c:413 exiting_irq arch/x86/include/asm/apic.h:536 [inline] smp_apic_timer_interrupt+0x14a/0x570 arch/x86/kernel/apic/apic.c:1062 apic_timer_interrupt+0xf/0x20 arch/x86/entry/entry_64.S:807 </IRQ> RIP: 0010:native_safe_halt+0x2/0x10 arch/x86/include/asm/irqflags.h:58 Code: ff ff ff 48 89 c7 48 89 45 d8 e8 59 0c a1 fa 48 8b 45 d8 e9 ce fe ff ff 48 89 df e8 48 0c a1 fa eb 82 90 90 90 90 90 90 fb f4 <c3> 0f 1f 00 66 2e 0f 1f 84 00 00 00 00 00 f4 c3 90 90 90 90 90 90 RSP: 0018:ffff8880a98afd78 EFLAGS: 00000286 ORIG_RAX: ffffffffffffff13 RAX: 1ffffffff1125061 RBX: ffff8880a989c340 RCX: 0000000000000000 RDX: dffffc0000000000 RSI: 0000000000000001 RDI: ffff8880a989cbbc RBP: ffff8880a98afda8 R08: ffff8880a989c340 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000001 R13: ffffffff889282f8 R14: 0000000000000001 R15: 0000000000000000 arch_cpu_idle+0x10/0x20 arch/x86/kernel/process.c:555 default_idle_call+0x36/0x90 kernel/sched/idle.c:93 cpuidle_idle_call kernel/sched/idle.c:153 [inline] do_idle+0x386/0x570 kernel/sched/idle.c:262 cpu_startup_entry+0x1b/0x20 kernel/sched/idle.c:353 start_secondary+0x404/0x5c0 arch/x86/kernel/smpboot.c:271 secondary_startup_64+0xa4/0xb0 arch/x86/kernel/head_64.S:243 Kernel Offset: disabled Rebooting in 86400 seconds.. Fixes: 79861919 ("tcp: fix TCP_REPAIR xmit queue setup") Signed-off-by:
Eric Dumazet <edumazet@google.com> Reported-by:
syzbot <syzkaller@googlegroups.com> Cc: Andrey Vagin <avagin@openvz.org> Cc: Soheil Hassas Yeganeh <soheil@google.com> Cc: Neal Cardwell <ncardwell@google.com> Acked-by:
Soheil Hassas Yeganeh <soheil@google.com> Acked-by:
Neal Cardwell <ncardwell@google.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Eric Dumazet authored
syzbot was able to trigger another soft lockup [1] I first thought it was the O(N^2) issue I mentioned in my prior fix (f657d22ee1f "net/x25: do not hold the cpu too long in x25_new_lci()"), but I eventually found that x25_bind() was not checking SOCK_ZAPPED state under socket lock protection. This means that multiple threads can end up calling x25_insert_socket() for the same socket, and corrupt x25_list [1] watchdog: BUG: soft lockup - CPU#0 stuck for 123s! [syz-executor.2:10492] Modules linked in: irq event stamp: 27515 hardirqs last enabled at (27514): [<ffffffff81006673>] trace_hardirqs_on_thunk+0x1a/0x1c hardirqs last disabled at (27515): [<ffffffff8100668f>] trace_hardirqs_off_thunk+0x1a/0x1c softirqs last enabled at (32): [<ffffffff8632ee73>] x25_get_neigh+0xa3/0xd0 net/x25/x25_link.c:336 softirqs last disabled at (34): [<ffffffff86324bc3>] x25_find_socket+0x23/0x140 net/x25/af_x25.c:341 CPU: 0 PID: 10492 Comm: syz-executor.2 Not tainted 5.0.0-rc7+ #88 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 RIP: 0010:__sanitizer_cov_trace_pc+0x4/0x50 kernel/kcov.c:97 Code: f4 ff ff ff e8 11 9f ea ff 48 c7 05 12 fb e5 08 00 00 00 00 e9 c8 e9 ff ff 90 90 90 90 90 90 90 90 90 90 90 90 90 55 48 89 e5 <48> 8b 75 08 65 48 8b 04 25 40 ee 01 00 65 8b 15 38 0c 92 7e 81 e2 RSP: 0018:ffff88806e94fc48 EFLAGS: 00000286 ORIG_RAX: ffffffffffffff13 RAX: 1ffff1100d84dac5 RBX: 0000000000000001 RCX: ffffc90006197000 RDX: 0000000000040000 RSI: ffffffff86324bf3 RDI: ffff88806c26d628 RBP: ffff88806e94fc48 R08: ffff88806c1c6500 R09: fffffbfff1282561 R10: fffffbfff1282560 R11: ffffffff89412b03 R12: ffff88806c26d628 R13: ffff888090455200 R14: dffffc0000000000 R15: 0000000000000000 FS: 00007f3a107e4700(0000) GS:ffff8880ae800000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007f3a107e3db8 CR3: 00000000a5544000 CR4: 00000000001406f0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: __x25_find_socket net/x25/af_x25.c:327 [inline] x25_find_socket+0x7d/0x140 net/x25/af_x25.c:342 x25_new_lci net/x25/af_x25.c:355 [inline] x25_connect+0x380/0xde0 net/x25/af_x25.c:784 __sys_connect+0x266/0x330 net/socket.c:1662 __do_sys_connect net/socket.c:1673 [inline] __se_sys_connect net/socket.c:1670 [inline] __x64_sys_connect+0x73/0xb0 net/socket.c:1670 do_syscall_64+0x103/0x610 arch/x86/entry/common.c:290 entry_SYSCALL_64_after_hwframe+0x49/0xbe RIP: 0033:0x457e29 Code: ad b8 fb ff c3 66 2e 0f 1f 84 00 00 00 00 00 66 90 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 0f 83 7b b8 fb ff c3 66 2e 0f 1f 84 00 00 00 00 RSP: 002b:00007f3a107e3c78 EFLAGS: 00000246 ORIG_RAX: 000000000000002a RAX: ffffffffffffffda RBX: 0000000000000003 RCX: 0000000000457e29 RDX: 0000000000000012 RSI: 0000000020000200 RDI: 0000000000000005 RBP: 000000000073c040 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000246 R12: 00007f3a107e46d4 R13: 00000000004be362 R14: 00000000004ceb98 R15: 00000000ffffffff Sending NMI from CPU 0 to CPUs 1: NMI backtrace for cpu 1 CPU: 1 PID: 10493 Comm: syz-executor.3 Not tainted 5.0.0-rc7+ #88 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 RIP: 0010:__read_once_size include/linux/compiler.h:193 [inline] RIP: 0010:queued_write_lock_slowpath+0x143/0x290 kernel/locking/qrwlock.c:86 Code: 4c 8d 2c 01 41 83 c7 03 41 0f b6 45 00 41 38 c7 7c 08 84 c0 0f 85 0c 01 00 00 8b 03 3d 00 01 00 00 74 1a f3 90 41 0f b6 55 00 <41> 38 d7 7c eb 84 d2 74 e7 48 89 df e8 cc aa 4e 00 eb dd be 04 00 RSP: 0018:ffff888085c47bd8 EFLAGS: 00000206 RAX: 0000000000000300 RBX: ffffffff89412b00 RCX: 1ffffffff1282560 RDX: 0000000000000000 RSI: 0000000000000004 RDI: ffffffff89412b00 RBP: ffff888085c47c70 R08: 1ffffffff1282560 R09: fffffbfff1282561 R10: fffffbfff1282560 R11: ffffffff89412b03 R12: 00000000000000ff R13: fffffbfff1282560 R14: 1ffff11010b88f7d R15: 0000000000000003 FS: 00007fdd04086700(0000) GS:ffff8880ae900000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007fdd04064db8 CR3: 0000000090be0000 CR4: 00000000001406e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: queued_write_lock include/asm-generic/qrwlock.h:104 [inline] do_raw_write_lock+0x1d6/0x290 kernel/locking/spinlock_debug.c:203 __raw_write_lock_bh include/linux/rwlock_api_smp.h:204 [inline] _raw_write_lock_bh+0x3b/0x50 kernel/locking/spinlock.c:312 x25_insert_socket+0x21/0xe0 net/x25/af_x25.c:267 x25_bind+0x273/0x340 net/x25/af_x25.c:703 __sys_bind+0x23f/0x290 net/socket.c:1481 __do_sys_bind net/socket.c:1492 [inline] __se_sys_bind net/socket.c:1490 [inline] __x64_sys_bind+0x73/0xb0 net/socket.c:1490 do_syscall_64+0x103/0x610 arch/x86/entry/common.c:290 entry_SYSCALL_64_after_hwframe+0x49/0xbe RIP: 0033:0x457e29 Fixes: 90c27297 ("X.25 remove bkl in bind") Signed-off-by:
Eric Dumazet <edumazet@google.com> Cc: andrew hendry <andrew.hendry@gmail.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Hauke Mehrtens authored
This callback was removed some time ago, also remove the documentation. Fixes: 1b6dd556 ("net: dsa: Remove prepare phase for FDB") Signed-off-by:
Hauke Mehrtens <hauke@hauke-m.de> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Hangbin Liu authored
This reverts commit 5a2de63f ("bridge: do not add port to router list when receives query with source 0.0.0.0") and commit 0fe5119e ("net: bridge: remove ipv6 zero address check in mcast queries") The reason is RFC 4541 is not a standard but suggestive. Currently we will elect 0.0.0.0 as Querier if there is no ip address configured on bridge. If we do not add the port which recives query with source 0.0.0.0 to router list, the IGMP reports will not be about to forward to Querier, IGMP data will also not be able to forward to dest. As Nikolay suggested, revert this change first and add a boolopt api to disable none-zero election in future if needed. Reported-by:
Linus Lüssing <linus.luessing@c0d3.blue> Reported-by:
Sebastian Gottschall <s.gottschall@newmedia-net.de> Fixes: 5a2de63f ("bridge: do not add port to router list when receives query with source 0.0.0.0") Fixes: 0fe5119e ("net: bridge: remove ipv6 zero address check in mcast queries") Signed-off-by:
Hangbin Liu <liuhangbin@gmail.com> Acked-by:
Nikolay Aleksandrov <nikolay@cumulusnetworks.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Thadeu Lima de Souza Cascardo authored
Just like commit e2ba732a ("selftests: fib_tests: sleep after changing carrier"), wait one second to allow linkwatch to propagate the carrier change to the stack. There are two sets of carrier tests. The first slept after the carrier was set to off, and when the second set ran, it was likely that the linkwatch would be able to run again without much delay, reducing the likelihood of a race. However, if you run 'fib_tests.sh -t carrier' on a loop, you will quickly notice the failures. Sleeping on the second set of tests make the failures go away. Cc: David Ahern <dsahern@gmail.com> Signed-off-by:
Thadeu Lima de Souza Cascardo <cascardo@canonical.com> Reviewed-by:
David Ahern <dsahern@gmail.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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- 23 Feb, 2019 1 commit
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Mao Wenan authored
cards_found is a static variable, but when it enters atl2_probe(), cards_found is set to zero, the value is not consistent with last probe, so next behavior is not our expect. Signed-off-by:
Mao Wenan <maowenan@huawei.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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