Commits · 02b865f88b4e4f72d441c34e5aa4e5eebbd04fbb · Kirill Smelkov / linux

26 May, 2021 6 commits

drm/amdgpu: refine amdgpu_fru_get_product_info · 02b865f8

Jiansong Chen authored May 25, 2021

1. eliminate potential array index out of bounds.
2. return meaningful value for failure.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Jack Gui <Jack.Gui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

02b865f8

drm/amdgpu: Change IP init sequence to support PSP program IH_RB_CNTL on NV12 SRIOV · 2a4021cc

Peng Ju Zhou authored May 25, 2021

To enable PSP program IH_RB_CNTL,
the PSP IP should be initialized before IH IP, otherwise,
it will hit psp NULL pointer.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2a4021cc

drm/amdgpu: Fix an error code in kfd_mem_attach_dmabuf() · 71330557

Dan Carpenter authored May 25, 2021

If amdgpu_gem_prime_export() fails, then this code accidentally
returns zero/success instead of a negative error code.

Fixes: 5ac3c3e4 ("drm/amdgpu: Add DMA mapping of GTT BOs")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

71330557

drm/amdgpu: add missing unreserve on error · 3e06db4d

Dan Carpenter authored May 25, 2021

The amdgpu_bo_unreserve() has to be done on the error path as well.

Fixes: 9e5d2753 ("drm/amdgpu: Move kfd_mem_attach outside reservation")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

3e06db4d

drm/amdgpu: add judgement for dc support · abaf210c

Asher Song authored May 21, 2021

Drop DC initialization when DCN is harvested in VBIOS. The way
doesn't affect virtual display ip initialization.
Signed-off-by: Likun Gao  <Likun.Gao@amd.com>
Signed-off-by: Asher Song <Asher.Song@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

abaf210c

drm/amdgpu: fix typo · 0e9def21

tony.huang_cp authored May 24, 2021

change 'interupt' to 'interrupt'
Signed-off-by: tony.huang_cp <huangwentao@yulong.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

0e9def21

21 May, 2021 34 commits

drm/amd/amdkfd: Drop unnecessary NULL check after container_of · 6a593769

Guenter Roeck authored May 21, 2021

The first parameter passed to container_of() is the pointer to the work
structure passed to the worker and never NULL. The NULL check on the
result of container_of() is therefore unnecessary and misleading.
Remove it.

This change was made automatically with the following Coccinelle script.

@@
type t;
identifier v;
statement s;
@@

<+...
(
  t v = container_of(...);
|
  v = container_of(...);
)
  ...
  when != v
- if (\( !v \| v == NULL \) ) s
...+>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

6a593769

drm/amdgpu: Fix inconsistent indenting · f43ae2d1

Jiapeng Chong authored May 21, 2021

Eliminate the follow smatch warning:

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c:449
sdma_v5_0_ring_emit_mem_sync() warn: inconsistent indenting.
Reviewed-by: Christian König <christian.koenig@amd.com>
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

f43ae2d1

drm/amdgpu/apci: switch ATIF/ATCS probe order · e0fb14c8

Alex Deucher authored May 20, 2021

Try the handle from ATPX first since this is the most
common case.
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

e0fb14c8

drm/amdgpu/acpi: unify ATCS handling (v3) · 77bf762f

Alex Deucher authored May 19, 2021

Treat it like ATIF and check both the dGPU and APU for
the method.  This is required because ATCS may be hung
off of the APU in ACPI on A+A systems.

v2: add back accidently removed ACPI handle check.
v3: Fix incorrect atif check (Colin)
    Fix uninitialized variable (Colin)
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

77bf762f

drm/amdgpu/display: make backlight setting failure messages debug · cd11b58c

Alex Deucher authored May 21, 2021

Avoid spamming the log.  The backlight controller on DCN chips
gets powered down when the display is off, so if you attempt to
set the backlight level when the display is off, you'll get this
message.  This isn't a problem as we cache the requested backlight
level if it's adjusted when the display is off and set it again
during modeset.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: nicholas.choi@amd.com
Cc: harry.wentland@amd.com

cd11b58c

drm/amd/display: Fix GPU scaling regression by FS video support · b0781603

Nicholas Kazlauskas authored May 19, 2021

[Why]
FS video support regressed GPU scaling and the scaled buffer ends up
stuck in the top left of the screen at native size - full, aspect,
center scaling modes do not function.

This is because decide_crtc_timing_for_drm_display_mode() does not
get called when scaling is enabled.

[How]
Split recalculate timing and scaling into two different flags.

We don't want to call drm_mode_set_crtcinfo() for scaling, but we
do want to call it for FS video.

Optimize and move preferred_refresh calculation next to
decide_crtc_timing_for_drm_display_mode() like it used to be since
that's not used for FS video.

We don't need to copy over the VIC or polarity in the case of FS video
modes because those don't change.

Fixes: 6f59f229 ("drm/amd/display: Skip modeset for front porch change")

Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

b0781603

drm/amdgpu: Use preemptible placement for KFD · 5bb19893

Felix Kuehling authored May 18, 2021

KFD userptr BOs and SG BOs used for DMA mappings can be preempted with
CWSR. Therefore we can use preemptible placement and avoid unwanted
evictions due to GTT accounting.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

5bb19893

drm/amdgpu: Add new placement for preemptible SG BOs · b453e42a

Felix Kuehling authored May 05, 2021

SG BOs such as dmabuf imports and userptr BOs do not consume system
resources directly. Instead they point to resources owned elsewhere.
They typically get evicted by DMABuf move notifiers of MMU notifiers.
If those notifiers don't need to wait for hardware fences (i.e. the SG
BOs are used in a preemptible context), then we don't need to limit
them to the GTT size and we don't need TTM to evict them.

Create a new placement for such preemptible SG BOs that does not impose
artificial size limits and TTM evictions.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

b453e42a

drm/amd/display: Allow bandwidth validation for 0 streams. · 6abb3f43

Bindu Ramamurthy authored May 20, 2021

[Why]
Bandwidth calculations are triggered for non zero streams, and
in case of 0 streams, these calculations were skipped with
pstate status not being updated.

[How]
As the pstate status is applicable for non zero streams, check
added for allowing 0 streams inline with dcn internal bandwidth
validations.
Signed-off-by: Bindu Ramamurthy <bindu.r@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

6abb3f43

drm/amd/pm: fix return value in aldebaran_set_mp1_state() · 5051cb79

Feifei Xu authored May 20, 2021

For default cases,we should return 0. Otherwise resume will
abort because of the wrong return value.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

5051cb79

drm/amd/pm: Correct reserved uint32_t number in beige_goby_PPTable · c15e2739

Chengming Gui authored May 21, 2021

Correct reserved number according to the latest struct in drm-next
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

c15e2739