- 19 Feb, 2018 33 commits
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Mikita Lipski authored
Verify that the stream is master - and program only the slave displays Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Roman Li authored
With FBC enabled there was a potential null-deref on topology change due to hardcorded pipe index. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Yongqiang Sun authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Jerry (Fangzhi) Zuo authored
When topology changed and rehook up MST display to the same DP connector, need to take care of drm_dp_mst_port object. Due to the topology is changed, drm_dp_mst_port and corresponding i2c_algorithm object could be NULL in such situation. Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Roman Li authored
After reworking FBC init for dynamic mem alloc old FBC init code in DC became redundant. Removing it. Signed-off-by:
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Roman Li authored
- FBC init reworked to alloc memory based on display mode. - Removed asic-dependencies from dm Signed-off-by:
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Ken Chalmers authored
This allows Maximus emulation to more closely mirror actual silicon execution. * Enable pool->base.display_clock creation on Maximus. * Enable rest of dce110_apply_ctx_to_hw on Maximus. * Remove apply_ctx_to_hw_fpga (no longer necessary with the full dce110_apply_ctx_to_hw enabled). * Disable the dmcu->funcs->set_psr_wait_loop call in dce112_set_clock for Maximus (this was the only fix-up necessary after enabling dce110_apply_ctx_to_hw; everything else works unmodified on Maximus). Signed-off-by:
Ken Chalmers <ken.chalmers@amd.com> Reviewed-by:
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Ken Chalmers authored
Maximus testing now defaults to a 700 MHz emulated dispclk Signed-off-by:
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Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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Fengguang Wu authored
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c:281:2-3: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Fixes: 620f774f ("drm/amdgpu: separate VMID and PASID handling") CC: Christian König <christian.koenig@amd.com> Signed-off-by:
Fengguang Wu <fengguang.wu@intel.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Rex Zhu authored
Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
Reviewed-by:
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Alex Deucher authored
We only need to flush the HDP here, not invalidate the TLB. Reviewed-by:
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Alex Deucher authored
Separate tlb invalidation and hdp flushing and move the HDP flush to the caller. Reviewed-by:
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Alex Deucher authored
Needed to flush and invalidate the HDP block using the CPU. v2: use preferred register on soc15. Reviewed-by:
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Alex Deucher authored
Needed to flush and invalidate the HDP block using the CPU. Reviewed-by:
Samuel Li <Samuel.Li@amd.com>
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Alex Deucher authored
Needed to flush and invalidate the HDP block using the CPU. Reviewed-by:
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Alex Deucher authored
Needed to flush and invalidate the HDP block using the CPU. Reviewed-by:
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Alex Deucher authored
Needed to properly flush the HDP cache with the CPU from rather than the GPU. Reviewed-by:
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Andres Rodriguez authored
Reviewed-by:
Andres Rodriguez <andresx7@gmail.com> Signed-off-by:
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Andres Rodriguez authored
We follow the same approach as gfx8. The only changes are register access macros. Tested on vega10. The execution latency results fall within the expected ranges from the polaris10 data. Reviewed-by:
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Evan Quan authored
Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
V2: reuse the SMUThermal structure defined in pp_thermal.h Signed-off-by:
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Evan Quan authored
V2: move the SMU7Thermal structure to newly created header file Signed-off-by:
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Evan Quan authored
V2: new header file to hold the common SMU7Thermal structure Signed-off-by:
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Alex Deucher authored
Populate the hwmon temp range as part of thermal controller setup. Signed-off-by:
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Evan Quan authored
Added a new callback for asic specific backends to specify the temperature ranges. Signed-off-by:
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Evan Quan authored
This will be used by powerplay to update the dpm temp range structure used to interface with hwmon. Signed-off-by:
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Evan Quan authored
drm/amd/powerplay: correct PP_TemperatureRange member type since negative values are part of the valid range Signed-off-by:
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Evan Quan authored
other parameter Signed-off-by:
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Evan Quan authored
Unused. v2: squash in warning fix (Harry) Signed-off-by:
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Dmitry Rozhkov authored
printk format strings accepting a single subsequent argument are shorter thus easier to read. Instead of having format strings accepting 3 different arguments pointing to first 3 bytes of the same buffer rewrite the format string to accept only one argument - the buffer - with "%3ph" specifier. Signed-off-by:
Dmitry Rozhkov <dmitry.rozhkov@linux.intel.com> Suggested-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by:
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Julia Lawall authored
PP_ASSERT_WITH_CODE prints a newline at the end of the message string, so the message string does not need to include a newline explicitly. Done using Coccinelle. Signed-off-by:
Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by:
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- 15 Feb, 2018 3 commits
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
Add HDCP support to i915 drm driver. * tag 'topic/hdcp-2018-02-13' of git://anongit.freedesktop.org/drm/drm-misc: (26 commits) drm/i915: fix misalignment in HDCP register def drm/i915: Reauthenticate HDCP on failure drm/i915: Detect panel's hdcp capability drm/i915: Optimize HDCP key load drm/i915: Retry HDCP bksv read drm/i915: Connector info in HDCP debug msgs drm/i915: Stop encryption for repeater with no sink drm/i915: Handle failure from 2nd stage HDCP auth drm/i915: Downgrade hdcp logs from INFO to DEBUG_KMS drm/i915: Restore HDCP DRM_INFO when with no downstream drm/i915: Check for downstream topology errors drm/i915: Start repeater auth on READY/CP_IRQ drm/i915: II stage HDCP auth for repeater only drm/i915: Extending HDCP for HSW, BDW and BXT+ drm/i915/dp: Fix compilation of intel_dp_hdcp_check_link drm/i915: Only disable HDCP when it's active drm/i915: Don't allow HDCP on PORT E/F drm/i915: Implement HDCP for DisplayPort drm/i915: Implement HDCP for HDMI drm/i915: Add function to output Aksv over GMBUS ...
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for 4.17: UAPI Changes: - drm/vc4: Expose performance counters to userspace (Boris) Cross-subsystem Changes: - MAINTAINERS: Linus to maintain panel-arm-versatile in -misc (Linus) Core Changes: - Only use swiotlb when necessary (Chunming) Driver Changes: - drm/panel: Add support for ARM Versatile panels (Linus) - pl111: Improvements around versatile panel support (Linus) ---------------------------------------- Tagged on 2018-02-06: drm-misc-next for 4.17: UAPI Changes: - Validate mode flags + type (Ville) - Deprecate unused mode flags PIXMUX, BCAST (Ville) - Deprecate unused mode types BUILTIN, CRTC_C, CLOCK_C, DEFAULT (Ville) Cross-subsystem Changes: - MAINTAINERS: s/Daniel/Maarten/ for drm-misc (Daniel) Core Changes: - gem: Export gem functions for drivers to use (Samuel) - bridge: Introduce bridge timings in drm_bridge (Linus) - dma-buf: Allow exclusive fence to be bundled in fence array when calling reservation_object_get_fences_rcu (Christian) - dp: Add training pattern 4 and HBR3 support to dp helpers (Manasi) - fourcc: Add alpha bit to formats to avoid driver format LUTs (Maxime) - mode: Various cleanups + add new device-wide .mode_valid hook (Ville) - atomic: Fix state leak when non-blocking commits fail (Leo) NOTE: IIRC, this was cross-picked to -fixes so it might fall out - crc: Allow polling on the data fd (Maarten) Driver Changes: - bridge/vga-dac: Add THS8134* support (Linus) - tinydrm: Various MIPI DBI improvements/cleanups (Noralf) - bridge/dw-mipi-dsi: Cleanups + use create_packet helper (Brian) - drm/sun4i: Add Display Engine frontend support (Maxime) - drm/sun4i: Add zpos support + increase num planes from 2 to 4 (Maxime) - various: Use drm_mode_get_hv_timing() to fill plane clip rectangle (Ville) - stm: Add 8-bit clut support, add dsi phy v1.31 support, +fixes (Phillipe) Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Chunming Zhou <david1.zhou@amd.com> Cc: Samuel Li <Samuel.Li@amd.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Noralf Trønnes <noralf@tronnes.org> Cc: Brian Norris <briannorris@chromium.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Christian König <christian.koenig@amd.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Philippe Cornu <philippe.cornu@st.com> Cc: Leo (Sunpeng) Li <sunpeng.li@amd.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> * tag 'drm-misc-next-2018-02-13' of git://anongit.freedesktop.org/drm/drm-misc: (115 commits) drm/radeon: only enable swiotlb path when need v2 drm/amdgpu: only enable swiotlb alloc when need v2 drm: add func to get max iomem address v2 drm/vc4: Expose performance counters to userspace drm: Print the pid when debug logging an ioctl error. drm/stm: ltdc: remove non-alpha color formats on layer 2 for older hw drm/stm: ltdc: add non-alpha color formats drm/bridge/synopsys: dsi: Add 1.31 version support drm/bridge/synopsys: dsi: Add read feature drm/pl111: Support multiple endpoints on the CLCD drm/pl111: Support variants with broken VBLANK drm/pl111: Support variants with broken clock divider drm/pl111: Handle the Versatile RGB/BGR565 mode drm/pl111: Properly detect the ARM PL110 variants drm/panel: Add support for ARM Versatile panels drm/panel: Device tree bindings for ARM Versatile panels drm/bridge: Rename argument from crtc to bridge drm/crc: Add support for polling on the data fd. drm/sun4i: Use drm_mode_get_hv_timing() to populate plane clip rectangle drm/rcar-du: Use drm_mode_get_hv_timing() to populate plane clip rectangle ...
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git://anongit.freedesktop.org/drm/drm-intelDave Airlie authored
UAPI Changes: - Userspace whitelist register GEN9_SLICE_COMMON_ECO_CHICKEN1 for GLK (Kenneth) - Non-existent PMU counters are not placed to sysfs (Tvrtko) - Add a note to deprecate I915_SET_COLORKEY_NONE and ignore it (Ville) * Intel DDX never ended using it, and implementation was wonky Core Changes: - Moved away from struct timeval into ktime_t in prep for 2038 (Arnd) * Merged the i915 portion through drm-tip, no core dependencies Driver Changes: - Base support for Icelake and Icelake PCH (Anusha, Rodrigo, Mahesh, Paulo, James, Kelvin) - Add AUX-F port support for Cannonlake (Rodrigo) - New DMC firmware for 1.07 Cannonlake (Anusha) * Go to linux-firmware.git to get it - Reject non-cursor planes nearly (3 px) out of screen on GLK/CNL (Imre) - Y/Yf modifiers restored for SKL+ sprites (Ville) - Compressed framebuffer support for sprites (Ville) - Tune down overly aggressive shrinking (Chris) - Shrink kmem caches when GPU is idle (Chris) - EDID bit-banging fallback for HDMI EDID (Stefan) - Don't boost the GPU when the waited request is already running (Chris) - Avoid GLK/BXT CDCLK frequency locking timeouts (Imre) - Limit DP link rate according to VBT on CNL+ (Jani) - Skip post-reset request emission if the engine is not idle (Chris) - Report any link training error on a fixed eDP panel as errors (Manasi) - DSI panel fixes for Bay Trail (Hans) - Selftest additions and improvements (Chris, Matt) - DMA fence test additions and accompanying fixes (Chris) - Power domain vs. register access fix (Maarten) - Squelch warnings for people with teensy framebuffers (stride < 512) (Maarten) - Increase Render/Media power gating hysteresis for Gen9+ (Chris) - HDMI vswing display workaround for Gen9+ (Ville) - GuC code cleanup and lockdep fixes (Sagar, Michal Wa.) - Continuously run hangcheck for simplicity (Chris) - Execlist debugging improvements (Chris) - GuC debugging improvements (Sujaritha, Michal Wa., Sagar) - Command parser boundary checks (Michal Srb) - Add a workaround for 3DSTATE_SAMPLE_PATTERN on CNL (Rafael) - Fix PMU enabling race condition (Tvrtko) - Usual smaller testing and debugging improvements * tag 'drm-intel-next-2018-02-07' of git://anongit.freedesktop.org/drm/drm-intel: (158 commits) drm/i915: Update DRIVER_DATE to 20180207 drm/i915/pmu: Fix PMU enable vs execlists tasklet race drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern drm/i915/cmdparser: Do not check past the cmd length. drm/i915/cmdparser: Check reg_table_count before derefencing. drm/i915: Deprecate I915_SET_COLORKEY_NONE drm/i915: Skip post-reset request emission if the engine is not idle drm/i915/execlists: Move the reset bits to a more natural home drm/i915/selftests: Use a sacrificial context for hang testing drm/i915/selftests: Flush old resets between engines drm/i915/breadcrumbs: Drop request reference for the signaler thread drm/i915: Remove unbannable context spam from reset drm/i915/execlists: Remove the startup spam drm/i915: Show the GPU state when declaring wedged drm/i915: Always update the no_fbc_reason when disabling drm/i915: Add some newlines to intel_engine_dump() headers drm/i915: Report if an unbannable context is involved in a GPU hang drm/i915: Remove spurious DRM_ERROR for cancelled interrupts drm/i915/execlists: Flush GTIIR on clearing CS interrupts during reset drm/i915: reduce indent in pch detection ...
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- 13 Feb, 2018 3 commits
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Chunming Zhou authored
swiotlb expands our card accessing range, but its path always is slower than ttm pool allocation. So add condition to use it. v2: move a bit later Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
Monk Liu <monk.liu@amd.com> Reviewed-by:
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Chunming Zhou authored
get the max io mapping address of system memory to see if it is over our card accessing range. v2: move checking later Signed-off-by:
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Chunming Zhou authored
it will be used to check if the driver needs swiotlb v2: Don't use inline, instead, move function to drm_memory.c (Michel Daenzer <michel@daenzer.net>) Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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- 11 Feb, 2018 1 commit
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Linus Torvalds authored
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