- 30 Mar, 2017 40 commits
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Rex Zhu authored
start vce first then enable vce dpm. Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Alex Deucher authored
Used for fetching external GPU information. Signed-off-by: -
Alex Deucher authored
Used for fetching external GPU information. Signed-off-by: -
Leo Liu authored
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Christian König <christian.koenig@amd.com> Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
And initialize them Reviewed-by:
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Huang Rui authored
Acked-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Huang Rui authored
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Alex Deucher authored
Newer asics use different registers so abstract it. Reviewed-by:
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Rex Zhu authored
v2: agd: integrate Christian's comments. v3: print error message if call fails Reviewed-by:
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Alex Xie authored
This lets each asic set whichever flags it supports. Signed-off-by:
Alex Xie <AlexBin.Xie@amd.com> Reviewed-by:
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Alex Xie authored
Set asic specific gart pte flags in the gmc IP module for each asic. Signed-off-by:
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Huang Rui authored
This will be used for newer asics. Acked-by:
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Chunming Zhou authored
Necessary for new asics. Signed-off-by:
Chunming Zhou <David1.Zhou@amd.com> Reviewed-by:
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Alex Deucher authored
The contextID field (formerly known as src_data) of the IH vector stores client specific information about an interrupt. It was expanded from 32 bits to 128 on newer asics. Expand the src_id field to handle this. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
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Alex Deucher authored
Newer asics have a two levels of irq ids now: client id - the IP src id - the interrupt src within the IP v2: integrated Christian's comments. v3: fix rebase fail in SI and CIK Signed-off-by:
Ken Wang <Qingqing.Wang@amd.com> Reviewed-by:
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Ken Wang authored
Newer asics need 64 bit doorbells. v2: fix comment (Nils) Reviewed-by:
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Ken Wang authored
Newer asics need 64 bit writeback slots. Reviewed-by:
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Ken Wang authored
Newer asics need 64 bit wptrs. If the wptr is now smaller than the rptr that doesn't indicate a wrap-around anymore. v2: integrate Christian's comments. Signed-off-by:
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Junwei Zhang authored
v2: agd: move apertures to mc structure Signed-off-by:
Flora Cui <Flora.Cui@amd.com> Reviewed-by:
Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by:
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Daniel Vetter authored
Again no apparent explanation for the split except hysterical raisins. Merging them also makes it a bit more obviuos what's going on wrt the runtime pm refdancing. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: amd-gfx@lists.freedesktop.org Reviewed-by:
Daniel Vetter <daniel.vetter@intel.com> Signed-off-by:
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Daniel Vetter authored
Again no apparent explanation for the split except hysterical raisins. Merging them also makes it a bit more obviuos what's going on wrt the runtime pm refdancing. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: amd-gfx@lists.freedesktop.org Reviewed-by:
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Andres Rodriguez authored
This information is intended to provide the required data to associate amdgpu tracepoints with their corresponding dma_fence_* events. Reviewed-by:
Andres Rodriguez <andresx7@gmail.com> Signed-off-by:
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Andres Rodriguez authored
Most of the traces have uniform format except for two of them. Having all the traces match makes it simple to run awk on the ftrace output. Reviewed-by:
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Xiangliang Yu authored
Because different HWs have different definition for CE & DE meta data, follow mqd design to move the structures to vi_structs.h. And change the prefix from amdgpu to vi as the structures is only for VI family. Signed-off-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by:
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Junshan Fang authored
Signed-off-by:
Junshan Fang <Junshan.Fang@amd.com> Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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Alex Deucher authored
Was missed when polaris12 support was added. Signed-off-by: -
Christian König authored
Not used in a while. Signed-off-by:
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Eric Huang authored
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Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by:
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Eric Huang authored
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Eric Huang authored
Disable avfs to make voltage change take effect. Signed-off-by:
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Andy Shevchenko authored
There is no need to repeat information that printed by PCI core at boot time. Besides that printing was potentially wrong since resource_size_t might be bigger than 32 bits and there is a dedicated specifier for such type, i.e. %pap. Someone can fix it and use even better approach, i.e. %pR. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by:
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Rex Zhu authored
v2: fix merge error. Signed-off-by:
Xiaojie Yuan <Xiaojie.Yuan@amd.com> Reviewed-by:
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Christian König authored
We completely bypass the HDP now. Signed-off-by:
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