- 01 Jul, 2008 35 commits
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Andrew Lewis authored
On PowerPC processors with non-coherent cache architectures the DMA subsystem calls invalidate_dcache_range() before performing a DMA read operation. If the address and length of the DMA buffer are not aligned to a cache-line boundary this can result in memory outside of the DMA buffer being invalidated in the cache. If this memory has an uncommitted store then the data will be lost and a subsequent read of that address will result in an old value being returned from main memory. Only when the DMA buffer starts on a cache-line boundary and is an exact mutiple of the cache-line size can invalidate_dcache_range() be called, otherwise flush_dcache_range() must be called. flush_dcache_range() will first flush uncommitted writes, and then invalidate the cache. Signed-off-by: Andrew Lewis <andrew-lewis at netspace.net.au> Signed-off-by:Paul Mackerras <paulus@samba.org>
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Kumar Gala authored
Since most bootloaders or wrappers tend to update or add some information to the .dtb they a handled they need some working space to do that in. By default add 1K of padding via a default setting of DTS_FLAGS. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
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Michael Neuling authored
Add CONFIG_VSX config build option. Must compile with POWER4, FPU and ALTIVEC. Signed-off-by:
Michael Neuling <mikey@neuling.org> Signed-off-by:
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Michael Neuling authored
This patch extends the floating point save and restore code to use the VSX load/stores when VSX is available. This will make FP context save/restore marginally slower on FP only code, when VSX is available, as it has to load/store 128bits rather than just 64bits. Mixing FP, VMX and VSX code will get constant architected state. The signals interface is extended to enable access to VSR 0-31 doubleword 1 after discussions with tool chain maintainers. Backward compatibility is maintained. The ptrace interface is also extended to allow access to VSR 0-31 full registers. Signed-off-by:
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Michael Neuling authored
This adds the macros for the VSX load/store instruction as most binutils are not going to support this for a while. Also add VSX register save/restore macros and vsr[0-63] register definitions. Signed-off-by:
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Michael Neuling authored
Add a VSX CPU feature. Also add code to detect if VSX is available from the device tree. Signed-off-by:
Joel Schopp <jschopp@austin.ibm.com> Signed-off-by:
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Michael Neuling authored
The layout of the new VSR registers and how they overlap on top of the legacy FPR and VR registers is: VSR doubleword 0 VSR doubleword 1 ---------------------------------------------------------------- VSR[0] | FPR[0] | | ---------------------------------------------------------------- VSR[1] | FPR[1] | | ---------------------------------------------------------------- | ... | | | ... | | ---------------------------------------------------------------- VSR[30] | FPR[30] | | ---------------------------------------------------------------- VSR[31] | FPR[31] | | ---------------------------------------------------------------- VSR[32] | VR[0] | ---------------------------------------------------------------- VSR[33] | VR[1] | ---------------------------------------------------------------- | ... | | ... | ---------------------------------------------------------------- VSR[62] | VR[30] | ---------------------------------------------------------------- VSR[63] | VR[31] | ---------------------------------------------------------------- VSX has 64 128bit registers. The first 32 regs overlap with the FP registers and hence extend them with and additional 64 bits. The second 32 regs overlap with the VMX registers. This commit introduces the thread_struct changes required to reflect this register layout. Ptrace and signals code is updated so that the floating point registers are correctly accessed from the thread_struct when CONFIG_VSX is enabled. Signed-off-by: -
Michael Neuling authored
Make load_up_fpu and load_up_altivec callable so they can be reused by the VSX code. Signed-off-by:
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Michael Neuling authored
Move the altivec_unavailable code, to make room at 0xf40 where the vsx_unavailable exception will be. Signed-off-by:
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Michael Neuling authored
We are going to change where the floating point registers are stored in the thread_struct, so in preparation add some macros to access the floating point registers. Update all code to use these new macros. Signed-off-by:
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Michael Neuling authored
If we set the SPE MSR bit in save_user_regs we can blow away the VEC bit. This doesn't matter in reality as they are in fact the same bit but looks bad. Also, when we add VSX in a later patch, we need to be able to set two separate MSR bits here. Signed-off-by:
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Tony Breeds authored
Currently we set the start of the .text section to be 4Mb for pSeries. In situations where the zImage is > 8Mb we'll fail to boot (due to overlapping with OF). Move .text in a zImage from 4MB to 64MB (well past OF). We still will not be able to load large zImage unless we also move OF, to that end, add a note to the zImage ELF to move OF to 32Mb. If this is the very first kernel booted then we'll need to move OF manually by setting real-base. Signed-off-by:
Tony Breeds <tony@bakeyournoodle.com> Signed-off-by:
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Michael Ellerman authored
Use an alternative feature section in _switch. There are three cases handled here, either we don't have an SLB, in which case we jump over the entire code section, or if we do we either do or don't have 1TB segments. Boot tested on Power3, Power5 and Power5+. Signed-off-by:
Michael Ellerman <michael@ellerman.id.au> Signed-off-by:
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Michael Ellerman authored
This commit adds tests of the feature fixup code, they are run during boot if CONFIG_FTR_FIXUP_SELFTEST=y. Some of the tests manually invoke the patching routines to check their behaviour, and others use the macros and so are patched during the normal patching done during boot. Because we have two sets of macros with different names, we use a macro to generate the test of the macros, very niiiice. Signed-off-by:
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Michael Ellerman authored
This commit adds the logic to patch alternative sections. This is fairly straightforward, except for branches. Relative branches that jump from inside the else section to outside of it need to be translated as they're moved, otherwise they will jump to the wrong location. Signed-off-by:
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Michael Ellerman authored
The current feature section logic only supports nop'ing out code, this means if you want to choose at runtime between instruction sequences, one or both cases will have to execute the nop'ed out contents of the other section, eg: BEGIN_FTR_SECTION or 1,1,1 END_FTR_SECTION_IFSET(FOO) BEGIN_FTR_SECTION or 2,2,2 END_FTR_SECTION_IFCLR(FOO) and the resulting code will be either, or 1,1,1 nop or, nop or 2,2,2 For small code segments this is fine, but for larger code blocks and in performance criticial code segments, it would be nice to avoid the nops. This commit starts to implement logic to allow the following: BEGIN_FTR_SECTION or 1,1,1 FTR_SECTION_ELSE or 2,2,2 ALT_FTR_SECTION_END_IFSET(FOO) and the resulting code will be: or 1,1,1 or, or 2,2,2 We achieve this by extending the existing FTR macros. The current feature section semantic just becomes a special case, ie. if the else case is empty we nop out the default case. The key limitation is that the size of the else case must be less than or equal to the size of the default case. If the else case is smaller the remainder of the section is nop'ed. We let the linker put the else case code in with the rest of the text, so that relative branches from the else case are more likley to link, this has the disadvantage that we can't free the unused else cases. This commit introduces the required macro and linker script changes, but does not enable the patching of the alternative sections. We also need to update two hand-made section entries in reg.h and timex.h Signed-off-by:
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Michael Ellerman authored
Currently we have three versions of MAKE_FTR_SECTION_ENTRY(), the macro that generates a feature section entry. There is 64bit version, a 32bit version and version for 32bit code built with a 64bit kernel. Rather than triplicating (?) the MAKE_FTR_SECTION_ENTRY() logic, we can move the 64bit/32bit differences into separate macros, and then only have one version of MAKE_FTR_SECTION_ENTRY(). Signed-off-by:
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Michael Ellerman authored
The CPU and firmware feature fixup macros are currently spread across three files, firmware.h, cputable.h and asm-compat.h. Consolidate them into their own file, feature-fixups.h Signed-off-by:
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Michael Ellerman authored
The logic to patch CPU feature sections lives in cputable.c, but these days it's used for CPU features as well as firmware features. Move it into it's own file for neatness and as preparation for some additions. While we're moving the code, we pull the loop body logic into a separate routine, and remove a comment which doesn't apply anymore. Signed-off-by:
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Michael Ellerman authored
A bunch of code has hard-coded the value for a "nop" instruction, it would be nice to have a #define for it. Signed-off-by:
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Michael Ellerman authored
Add tests of the existing code patching routines, as well as the new routines added in the last commit. The self-tests are run late in boot when CONFIG_CODE_PATCHING_SELFTEST=y, which depends on DEBUG_KERNEL=y. Signed-off-by:
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Michael Ellerman authored
This commit adds some new routines for patching code, which will be used in a following commit. Signed-off-by:
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Michael Ellerman authored
Because function pointers point to different things on 32-bit vs 64-bit, add a macro that deals with dereferencing the OPD on 64-bit. The soon to be merged ftrace wants this, as well as other code I am working on. Signed-off-by:
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Michael Ellerman authored
If you pass a target value to create_branch() which is more than 32MB - 4, or - 32MB away from the branch site, then it's impossible to create an immediate branch. The current code doesn't check, which will lead to us creating a branch to somewhere else - which is bad. For code that cares to check we return 0, which is easy to check for, and for code that doesn't at least we'll be creating an illegal instruction, rather than a branch to some random address. Signed-off-by:
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Michael Ellerman authored
Currently create_branch() creates a branch instruction for you, and patches it into the call site. In some circumstances it would be nice to be able to create the instruction and patch it later, and also some code might want to check for errors in the branch creation before doing the patching. A future commit will change create_branch() to check for errors. For callers that don't care, replace create_branch() with patch_branch(), which just creates the branch and patches it directly. While we're touching all the callers, change to using unsigned int *, as this seems to match usage better. That allows (and requires) us to remove the volatile in the definition of vector in powermac/smp.c and mpc86xx_smp.c, that's correct because now that we're passing vector as an unsigned int * the compiler knows that it's value might change across the patch_branch() call. Signed-off-by:
Jon Loeliger <jdl@freescale.com> Signed-off-by:
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Michael Ellerman authored
We currently have a few routines for patching code in asm/system.h, because they didn't fit anywhere else. I'd like to clean them up a little and add some more, so first move them into a dedicated C file - they don't need to be inlined. While we're moving the code, drop create_function_call(), it's intended caller never got merged and will be replaced in future with something different. Signed-off-by:
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Julia Lawall authored
This makes two changes: * As noted by Akinobu Mita in patch b1fceac2, alloc_bootmem never returns NULL and always returns a zeroed region of memory. Thus the error checking code and memset after the call to alloc_bootmem are not necessary. * The old error handling code consisted of setting a global variable to NULL and returning an error code, which could cause previously allocated resources never to be freed. The patch adds calls to appropriate resource deallocation functions. Signed-off-by:
Julia Lawall <julia@diku.dk> Signed-off-by:
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Adrian Bunk authored
This makes asm/elf.h export less non-userspace stuff to userspace. Signed-off-by:
Adrian Bunk <bunk@kernel.org> Signed-off-by:
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Adrian Bunk authored
asm/asm-compat.h doesn't seem to be intended for userspace usage. Signed-off-by:
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Adrian Bunk authored
This contains the following cleanups: - make the following needlessly global code static: - adb.c: adb_controller - adb.c: adb_init() - adbhid.c: adb_to_linux_keycodes[] (also make it const) - via-pmu68k.c: backlight_level - via-pmu68k.c: backlight_enabled - remove the following unused code: - via-pmu68k.c: sleep_notifier_list Signed-off-by:
Geert Uytterhoeven <geert@linux-m68k.org> Acked-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
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Kumar Gala authored
Refactor common code between ppc32 and ppc64 module handling into a shared filed. Signed-off-by:
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Dave Kleikamp authored
Signed-off-by:
Dave Kleikamp <shaggy@linux.vnet.ibm.com> Cc: Jon Tollefson <kniht@linux.vnet.ibm.com> Cc: Adam Litke <agl@us.ibm.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
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Joel Schopp authored
Add the bits to the architecture-vec so that ibm,client-architecture lets the firmware know we support the 2.06 architecture. Signed-off-by:
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Joel Schopp authored
Add an entry for Power7 architected mode and add "(raw)" to Power7 raw mode to distinguish it more clearly. Signed-off-by:
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Paul Mackerras authored
At present, if we have a kernel with a 64kB page size, and some process maps something that has to be mapped with 4kB pages (such as a cache-inhibited mapping on POWER5+, or the eHCA infiniband queue-pair pages), we change the process to use 4kB pages everywhere. This hurts the performance of HPC programs that access eHCA from userspace. With this patch, the kernel will only demote the slice(s) containing the eHCA or cache-inhibited mappings, leaving the remaining slices able to use 64kB hardware pages. This also changes the slice_get_unmapped_area code so that it is willing to place a 64k-page mapping into (or across) a 4k-page slice if there is no better alternative, i.e. if the program specified MAP_FIXED or if there is not sufficient space available in slices that are either empty or already have 64k-page mappings in them. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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- 30 Jun, 2008 5 commits
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Michael Neuling authored
Add a cputable entry for the POWER7 processor. Also tell firmware that we know about POWER7. Signed-off-by:
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Scott Wood authored
This was pointed out by Detlev Zundel when this code was being added to U-boot. Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
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Becky Bruce authored
While working on the 36-bit physical support, I noticed that there was exactly one line of code that actually referenced the bitfields. So I got rid of them and redefined ppc_bat as a struct of 2 u32's: batu and batl. I also got rid of the previous union that held the bitfield structs and a word representation of the batu/l values. This seems like a nicer solution than adding in a bunch of new bitfields to support extended bat addressing that would never get used, and just leaving the struct as-is would have been incomplete in the face of large physical addressing. Signed-off-by:
Becky Bruce <becky.bruce@freescale.com> Signed-off-by:
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Becky Bruce authored
Currently, the physical address is an unsigned long, but it should be phys_addr_t in set_bat, [v/p]_mapped_by_bat. Also, create a macro that can convert a large physical address into the correct format for programming the BAT registers. Signed-off-by:
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Becky Bruce authored
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