- 17 Aug, 2021 1 commit
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Linus Walleij authored
Merge tag 'samsung-pinctrl-5.15' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v5.15 1. Fix number of pins in one GPIO pin bank. 2. Add support for Exynos850 SoC (Exynos3830).
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- 16 Aug, 2021 10 commits
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Linus Walleij authored
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Jianqun Xu authored
With the patch to separate the gpio driver from the pinctrl driver, now the pinctrl-rockchip can drop the gpio related codes now. Signed-off-by:
Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20210816012146.1119289-1-jay.xu@rock-chips.comSigned-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Jianqun Xu authored
There has spin lock for irq set type already, so drop irq_gc_lock and irq_gc_unlock. Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
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Jianqun Xu authored
The next version gpio controller on SoCs like rk3568 have more write mask bits for registers. Signed-off-by:
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Jianqun Xu authored
Store register offsets in the struct rockchip_gpio_regs, this patch prepare for the driver update for new gpio controller. Reviewed-by:
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Jianqun Xu authored
This patch add support for rockchip gpio controller, which is supported in pinctrl driver in the past. With this patch, the pinctrl-rockchip driver will drop gpio related codes and populate platform driver to gpio-rockchip. Signed-off-by:
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Jianqun Xu authored
In the past we only need on clock which name "pclk" for a gpio controller. In the new version gpio controller, there add some register to change debounce clock dynamic, so the dt node needs to add the second clock, we call it "dbclk". The clock property need 2 items on some rockchip chips such as RK3568 SoCs. Signed-off-by:
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Jianqun Xu authored
Store a pointer from the pinctrl device for the gpio bank. Signed-off-by:
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Jianqun Xu authored
Separate struct rockchip_pin_bank to pinctrl-rockchip.h file, which will be used by gpio-rockchip driver in the future. Signed-off-by:
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Jianqun Xu authored
Since gate and ungate pclk of gpio has very litte benifit for system power consumption, just keep it always ungate. Signed-off-by:
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- 13 Aug, 2021 4 commits
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.15 (take two) - Add pin control and GPIO support for the new RZ/G2L SoC.
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Lad Prabhakar authored
Add support for pin and gpio controller driver for RZ/G2L SoC. Based on a patch in the BSP by Hien Huynh <hien.huynh.px@renesas.com>. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210727112328.18809-3-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Sam Protsenko authored
Add Samsung Exynos850 SoC specific data to enable pinctrl support for all platforms based on Exynos850. Signed-off-by:
Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20210811114827.27322-3-semen.protsenko@linaro.org [krzysztof: lower-case the hex-numbers] Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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Sam Protsenko authored
Document compatible string for Exynos850 SoC. Nothing else is changed, as Exynos850 SoC uses already existing samsung pinctrl driver. Signed-off-by:
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- 12 Aug, 2021 1 commit
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Shyam Sundar S K authored
Adding Basavaraj and myself to the maintainers list for amd-pinctrl driver. Signed-off-by:
Basavaraj Natikar <Basavaraj.Natikar@amd.com> Signed-off-by:
Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Link: https://lore.kernel.org/r/20210812115322.765379-1-Shyam-sundar.S-k@amd.comSigned-off-by:
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- 11 Aug, 2021 17 commits
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Lakshmi Sowjanya D authored
About Intel Keem Bay: ------------------- Intel Keem Bay is a computer vision AI accelerator SoC based on ARM CPU. Documentation of Keem Bay: Documentation/vpu/vpu-stack-overview.rst. Pinctrl IP: ---------- The SoC has a customised pinmux controller IP which controls pin multiplexing and configuration. Keem Bay pinctrl IP is not based on and have nothing in common with the existing pinctrl drivers. The registers used are incompatible with the existing drivers, so it requires a new driver. Add pinctrl driver to enable pin control support in the Intel Keem Bay SoC. Co-developed-by:
Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> Signed-off-by:
Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> Signed-off-by:
Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> Reviewed-by:
Mark Gross <mgross@linux.intel.com> Reviewed-by:
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Lakshmi Sowjanya D authored
Add Device Tree bindings documentation for Intel Keem Bay SoC's pin controller. Add entry for INTEL Keem Bay pinctrl driver in MAINTAINERS file Co-developed-by:
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Yang Yingliang authored
It's not necessary to unregister pin controller device registered with devm_pinctrl_register() and using pinctrl_unregister() leads to a double free. Fixes: fa99e701 ("pinctrl: zynqmp: some code cleanups") Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Reviewed-by:
Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210729071905.3235953-1-yangyingliang@huawei.comSigned-off-by:
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satya priya authored
Remove the interrupts property as we no longer specify it. Signed-off-by:
satya priya <skakit@codeaurora.org> Acked-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1627910464-19363-4-git-send-email-skakit@codeaurora.orgSigned-off-by:
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satya priya authored
Convert Qualcomm PMIC GPIO bindings from .txt to .yaml format. Signed-off-by:
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Chen-Yu Tsai authored
The original binding submission for MT8195 pinctrl described the possible drive strength values in micro-amps in its description, but then proceeded to list register values in its device tree binding constraints. However, the macros used with the Mediatek pinctrl bindings directly specify the drive strength in micro-amps, instead of hardware register values. The current driver implementation in Linux does convert the value from micro-amps to hardware register values. This implementation is also used with MT7622 and MT8183, which use real world values in their device trees. Given the above, it was likely an oversight to use the raw register values in the binding. Correct the values in the binding. Also drop the description since the binding combined with its parent, pinctrl/pincfg.yaml, the binding is now self-describing. Fixes: 7f766389 ("dt-bindings: pinctrl: mt8195: add pinctrl file and binding document") Signed-off-by:
Chen-Yu Tsai <wenst@chromium.org> Acked-by:
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Linus Walleij authored
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Hsin-Yi Wang authored
Convert mt65xx, mt6796, mt7622, mt8183 bindings to yaml. Signed-off-by:
Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by:
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Hsin-Yi Wang authored
Move mt8183-pinfunc.h into include/dt-bindings/pinctrl so that we can include it in yaml examples. Signed-off-by:
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Hsin-Yi Wang authored
Move mt8135-pinfunc.h into include/dt-bindings/pinctrl so that we can include it in yaml examples. Signed-off-by:
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Paul Cercueil authored
Compute the max register from the GPIO chip offset and number of GPIO chips. This permits to read all registers from debugfs. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20210717174836.14776-3-paul@crapouillou.netSigned-off-by:
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Paul Cercueil authored
The ingenic_set_bias() function's "bias" argument is not a "enum pin_config_param", so its value should not be compared against values of that enum. This should fix the bias config not working on the X2000(E) SoCs. Fixes: 943e0da1 ("pinctrl: Ingenic: Add pinctrl driver for X2000.") Cc: <stable@vger.kernel.org> # v5.12 Signed-off-by:
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Paul Cercueil authored
Fix the pull up/down info for both the JZ4760 and JZ4770 SoCs, as the previous values sometimes contradicted what's written in the programming manual. Fixes: b5c23aa4 ("pinctrl: add a pinctrl driver for the Ingenic jz47xx SoCs") Cc: <stable@vger.kernel.org> # v4.12 Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
Add support for probing the pinctrl-ingenic driver on the X2100 SoC from Ingenic. Signed-off-by:
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/1627108604-91304-5-git-send-email-zhouyanjie@wanyeetech.comSigned-off-by:
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周琰杰 (Zhou Yanjie) authored
Add the pinctrl bindings for the X2100 SoC from Ingenic. Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
Add SSI pins support for the JZ4755 SoC and the JZ4760 SoC from Ingenic. Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
1.Rename the original "dmicx" ABIs to "dmic-ifx", since these devices have only one DMIC module which has multiple input interfaces. The original naming is easy to make users mistakenly think that the device has multiple dmic modules. Currently, in the mainline, no other devicetree out there is using the "sfc" ABI, so we should be able to replace it safely. 2.Rename the original "ssix-ce0" ABIs to "ssix-ce", since the X2000 have only one ce pin. The original naming is easy to make users mistakenly think that the device has multiple ce pins. Currently, in the mainline, no other devicetree out there is using the "ssix-ce0" ABIs, so we should be able to replace it safely. 3.Split the original "sfc" ABI into "sfc-data", "sfc-ce", "sfc-clk" to increase the flexibility when configuring the pins. Currently, in the mainline, no other devicetree out there is using the "sfc" ABI, so we should be able to replace it safely. 4.There is more than one compatible string in the match table, so renaming "ingenic_xxxx_of_match[]" to "ingenic_xxxx_of_matches" is more reasonable, and remove the unnecessary commas in "ingenic_gpio_of_matches[]" to reduce code size as much as possible. Signed-off-by:
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- 10 Aug, 2021 7 commits
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Randy Dunlap authored
Eliminate kernel-doc warnings in drivers/pinctrl/aspeed by using proper kernel-doc notation. Fixes these kernel-doc warnings: drivers/pinctrl/aspeed/pinmux-aspeed.c:61: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Query the enabled or disabled state for a mux function's signal on a pin drivers/pinctrl/aspeed/pinctrl-aspeed.c:135: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Search for the signal expression needed to enable the pin's signal for the Signed-off-by:Randy Dunlap <rdunlap@infradead.org> Reported-by:
kernel test robot <lkp@intel.com> Cc: Aditya Srivastava <yashsri421@gmail.com> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: linux-aspeed@lists.ozlabs.org Cc: openbmc@lists.ozlabs.org Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Acked-by:
Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210723034840.8752-1-rdunlap@infradead.orgSigned-off-by:
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Marc Zyngier authored
Casting a small array of u8 to an unsigned long is *never* OK: - it does funny thing when the array size is less than that of a long, as it accesses random places in the stack - it makes everything even more fun with a BE kernel Fix this by building the unsigned long used as a bitmap byte by byte, in a way that works across endianess and has no undefined behaviours. An extra BUILD_BUG_ON() catches the unlikely case where the array would be larger than a single unsigned long. Fixes: 1490d9f8 ("pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver") Signed-off-by:
Marc Zyngier <maz@kernel.org> Cc: stable@vger.kernel.org Cc: Amelie Delaunay <amelie.delaunay@foss.st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Link: https://lore.kernel.org/r/20210725180830.250218-1-maz@kernel.orgSigned-off-by:
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Alexandre Torgue authored
STM32MP135 SoC embeds 9 GPIO banks of 16 gpios each. Those GPIO banks contain same features as STM32MP157 GPIO banks except that each GPIO line of the STM32MP135 can be secured. Signed-off-by:
Alexandre Torgue <alexandre.torgue@foss.st.com> Acked-by: Arnd Bergmann <arnd@arndb.de Link: https://lore.kernel.org/r/20210723132810.25728-3-alexandre.torgue@foss.st.comSigned-off-by:
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Alexandre Torgue authored
New compatible to manage ball out and pin muxing of STM32MP135 SoC. Signed-off-by:
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Zhen Lei authored
The value of pcs->flags is not overwritten in function pcs_parse_bits_in_pinctrl_entry() and its subfunctions, so moving this check to the beginning of the function eliminates unnecessary rollback operations. Signed-off-by:
Zhen Lei <thunder.leizhen@huawei.com> Reviewed-by:
Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20210722033930.4034-3-thunder.leizhen@huawei.comSigned-off-by:
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Zhen Lei authored
Fix to return -ENOTSUPP instead of 0 when PCS_HAS_PINCONF is true, which is the same as that returned in pcs_parse_pinconf(). Fixes: 4e7e8017 ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules") Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
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Bjorn Andersson authored
The SC8180x platform comes with PMC8180 and PMC8180c, add support for the GPIO controller in these PMICs. Signed-off-by:
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