- 19 Feb, 2018 40 commits
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SivapiriyanKumarasamy authored
Lock top_pipe when doing update plane addr for split pipe freesync case Signed-off-by:
SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Harry Wentland authored
There's no good place in DC to cover all place where stream signal should be updated. update_stream_signal depends on timing which comes from DM. Signed-off-by:
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Leo (Sunpeng) Li authored
If crc is disabled, early return when getting crc's. That way, we avoid reading extra registers within the pflip high irq. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
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Yongqiang Sun authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Ken Chalmers authored
Signed-off-by:
Ken Chalmers <ken.chalmers@amd.com> Signed-off-by:
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Duke Du authored
Signed-off-by:
Duke Du <Duke.Du@amd.com> Signed-off-by:
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Harry Wentland authored
We're currently not using this. v2: More files and includes to remove. Signed-off-by:
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Alex Deucher authored
The IP soft reset interface is for per IP reset but it was being abused for adapter reset on soc15 asics. Adjust the interface to make it explicit. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
This way we can make all of the IP specific functions static, and we only need a single entry point into the PSP IP modules. Reviewed-by:
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Christian König authored
Instead of repeating this multiple times. Signed-off-by:
Monk Liu <monk.liu@amd.com> Signed-off-by:
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Christian König authored
Reserve VA space at the top for older generations as well. Signed-off-by:
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Christian König authored
1MB should be more than enough, currently we use about 8K. Signed-off-by:
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Samuel Li authored
Add display to the name for consistency. Signed-off-by:
Samuel Li <Samuel.Li@amd.com> Acked-by:
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Samuel Li authored
Add display to the name for consistency. Signed-off-by:
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Samuel Li authored
Add display to the name for consistency. Signed-off-by:
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Samuel Li authored
Rename as amdgpu_display_update_priority for consistency. Signed-off-by:
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Samuel Li authored
Add display to the name for consistency. Signed-off-by:
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Samuel Li authored
Add display to the name for consistency. Signed-off-by:
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Samuel Li authored
Add display to the name for consistency. Signed-off-by:
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Samuel Li authored
Add display to the name for consistency. Signed-off-by:
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Samuel Li authored
Add display to the name for consistency. Signed-off-by:
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Samuel Li authored
Add display to the name for consistency. Signed-off-by:
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Samuel Li authored
Add display to the name for consistency. Signed-off-by:
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Samuel Li authored
Add display to the name for consistency. Signed-off-by:
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Christian König authored
All HDP invalidation and most flush can now be replaced by the generic ASIC function. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Christian König authored
When ring special operations aren't available we can fallback to the generic ASIC operations. Signed-off-by:
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Christian König authored
This adds an optional ring to the invalidate_hdp and flush_hdp callbacks. If the ring isn't specified or the emit_wreg function not available the HDP operation will be done with the CPU otherwise by writing on the ring. Signed-off-by:
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Rex Zhu authored
when Overdrive voltage, need to disable AVFS. when OverDriv engine clock, need to recalculate AVFS voltage by disable/enable avfs feature. Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
Delete old OD type code path when populate clk. Reviewed-by:
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Rex Zhu authored
v2: - check clk against OverDrive limits from VBIOS - set OD flag when user commit the setting. Reviewed-by: -
Rex Zhu authored
Not supported on APUs or Iceland. and still not enabled on CI. Reviewed-by:
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Rex Zhu authored
Check vbios to determine whether we can enable OD Reviewed-by:
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Rex Zhu authored
when cat pp_od_clk_voltage it show OD_SCLK: 0: 300Mhz 800 mV 1: 466Mhz 818 mV 2: 751Mhz 824 mV 3: 1019Mhz 987 mV 4: 1074Mhz 1037 mV 5: 1126Mhz 1087 mV 6: 1169Mhz 1137 mV 7: 1206Mhz 1150 mV OD_MCLK: 0: 300Mhz 800 mV 1: 1650Mhz 1000 mV echo "s/m level clock voltage" to change sclk/mclk's clock and voltage echo "r" to restore default value. echo "c" to commit the user setting. Reviewed-by:
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Rex Zhu authored
Add odn_edit_dpm_table function points for setting user assigned clock/voltage. Reviewed-by:
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Alex Deucher authored
The preinstall callback didn't do anything because not all of the IPs were initialized when it was called. Move the postinstall setup into sequence in the driver. The uninstall callback disabled all interrupt source, but it got called too late in the driver sequence and caused problems with IPs who already freed the relevant data structures. Move the call into the right place in the driver sequence. Acked-by:
Mikita Lipski <mikita.lipski@amd.com> Signed-off-by:
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Alex Deucher authored
COMPUTER -> COMPUTE Reviewed-by:
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Hawking Zhang authored
Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
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Hawking Zhang authored
Signed-off-by:
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Hawking Zhang authored
Signed-off-by:
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Hawking Zhang authored
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