- 19 Jan, 2011 7 commits
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Jeff Layton authored
Reviewed-by:
Suresh Jayaraman <sjayaraman@suse.de> Reviewed-by:
Pavel Shilovsky <piastryyy@gmail.com> Signed-off-by:
Jeff Layton <jlayton@redhat.com> Signed-off-by:
Steve French <sfrench@us.ibm.com>
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Jeff Layton authored
In later patches, we're going to need to have finer-grained control over the addition and removal of these structs from the pending_mid_q and we'll need to be able to call the destructor while holding the spinlock. Move the locked sections out of both routines and into the callers. Fix up current callers of DeleteMidQEntry to call a new routine that dequeues the entry and then destroys it. Reviewed-by:
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Jeff Layton authored
It's an atomic_t and the code accesses the "counter" field in it directly instead of using atomic_read(). It also is sometimes accessed under a spinlock and sometimes not. Move it out of the spinlock since we don't need belt-and-suspenders for something that's just informational. Reviewed-by:
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Jeff Layton authored
The cifsSesInfo pointer is only used to get at the server. Reviewed-by:
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Jeff Layton authored
The TCP_Server_Info is refcounted and every SMB session holds a reference to it. Thus, smb_ses_list is always going to be empty when cifsd is coming down. This is dead code. Reviewed-by:
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Jeff Layton authored
If CIFSSMBWrite2 returns -EAGAIN, then the error should be considered temporary. CIFS should retry the write instead of setting an error on the mapping and returning. For WB_SYNC_ALL, just retry the write immediately. In the WB_SYNC_NONE case, call redirty_page_for_writeback on all of the pages that didn't get written out and then move on. Also, fix up the handling of a short write with a successful return code. MS-CIFS says that 0 bytes_written means ENOSPC or EFBIG. It doesn't mention what a short, but non-zero write means, so for now treat it as we would an -EAGAIN return. Reviewed-by:
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Pavel Shilovsky authored
When we get oplock break notification we should set the appropriate value of OplockLevel field in oplock break acknowledge according to the oplock level held by the client in this time. As we only can have level II oplock or no oplock in the case of oplock break, we should be aware only about clientCanCacheRead field in cifsInodeInfo structure. Also fix bug connected with wrong interpretation of OplockLevel field during oplock break notification processing. Signed-off-by:
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- 18 Jan, 2011 33 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/groeck/stagingLinus Torvalds authored
* 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/staging: hwmon: (lm93) Add support for LM94
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Linus Torvalds authored
Merge branch 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: perf: Validate cpu early in perf_event_alloc() perf: Find_get_context: fix the per-cpu-counter check perf: Fix contexted inheritance
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Linus Torvalds authored
Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86: Clear irqstack thread_info x86: Make relocatable kernel work with new binutils
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git://git.linux-mips.org/pub/scm/upstream-linusLinus Torvalds authored
* 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus: (26 commits) MIPS: Malta: enable Cirrus FB console MIPS: add CONFIG_VIRTUALIZATION for virtio support MIPS: Implement __read_mostly MIPS: ath79: add common WMAC device for AR913X based boards MIPS: ath79: Add initial support for the Atheros AP81 reference board MIPS: ath79: add common SPI controller device SPI: Add SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs MIPS: ath79: add common GPIO buttons device MIPS: ath79: add common watchdog device MIPS: ath79: add common GPIO LEDs device MIPS: ath79: add initial support for the Atheros PB44 reference board MIPS: ath79: utilize the MIPS multi-machine support MIPS: ath79: add GPIOLIB support MIPS: Add initial support for the Atheros AR71XX/AR724X/AR931X SoCs MIPS: jump label: Add MIPS support. MIPS: Use WARN() in uasm for better diagnostics. MIPS: Optimize TLB handlers for Octeon CPUs MIPS: Add LDX and LWX instructions to uasm. MIPS: Use BBIT instructions in TLB handlers MIPS: Declare uasm bbit0 and bbit1 functions. ...
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Guenter Roeck authored
This patch adds basic support for LM94 to the LM93 driver. LM94 specific sensors and features are not supported. Signed-off-by:
Guenter Roeck <guenter.roeck@ericsson.com> Acked-by:
Jean Delvare <khali@linux-fr.org>
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Oleg Nesterov authored
Starting from perf_event_alloc()->perf_init_event(), the kernel assumes that event->cpu is either -1 or the valid CPU number. Change perf_event_alloc() to validate this argument early. This also means we can remove the similar check in find_get_context(). Signed-off-by:
Oleg Nesterov <oleg@redhat.com> Acked-by:
Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Alan Stern <stern@rowland.harvard.edu> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Paul Mackerras <paulus@samba.org> Cc: Prasad <prasad@linux.vnet.ibm.com> Cc: Roland McGrath <roland@redhat.com> Cc: gregkh@suse.de Cc: stable@kernel.org LKML-Reference: <20110118161032.GC693@redhat.com> Signed-off-by:
Ingo Molnar <mingo@elte.hu>
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Oleg Nesterov authored
If task == NULL, find_get_context() should always check that cpu is correct. Afaics, the bug was introduced by 38a81da2 "perf events: Clean up pid passing", but even before that commit "&& cpu != -1" was not exactly right, -ESRCH from find_task_by_vpid() is not accurate. Signed-off-by:
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Aurelien Jarno authored
While most users of a physical Malta board are using the serial port as the console, a lot of QEMU users would prefer to interact with a graphical console. Enable the Cirrus FB support in the Malta default configuration to make that possible. Note that the default console will still be the serial port, users have to pass "console=tty0" to the kernel to use the Cirrus FB. Signed-off-by:
Aurelien Jarno <aurelien@aurel32.net> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2001/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Aurelien Jarno authored
Add CONFIG_VIRTUALIZATION to the MIPS architecture and include the the virtio code there. Used to enable the virtio drivers under QEMU. Signed-off-by:
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David Daney authored
Just do what everyone else is doing by placing __read_mostly things in the .data.read_mostly section. mips_io_port_base can not be read-only (const) and writable (__read_mostly) at the same time. One of them has to go, so I chose to eliminate the __read_mostly. It will still get stuck in a portion of memory that is not adjacent to things that are written, and thus not be on a dirty cache line, for whatever that is worth. Signed-off-by:
David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1702/Signed-off-by:
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Gabor Juhos authored
Add common platform_device and helper code to make the registration of the built-in wireless MAC easier on the Atheros AR9130/AR9132 based boards. Also register the WMAC device on the AR81 board. Signed-off-by:
Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Imre Kaloz <kaloz@openwrt.org>, Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1962/Signed-off-by:
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Gabor Juhos authored
Signed-off-by:
Imre Kaloz <kaloz@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1952/Signed-off-by:
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Gabor Juhos authored
Several boards are using the built-in SPI controller of the AR71XX/AR724X/AR913X SoCs. This patch adds common platform_device and helper code to register it. Additionally, the patch registers the SPI bus on the PB44 board. Signed-off-by:
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Gabor Juhos authored
The Atheros AR71XX/AR724X/AR913X SoCs have a built-in SPI controller. This patch implements a driver for that. Signed-off-by:
Grant Likely <grant.likely@secretlab.ca> Cc: linux-mips@linux-mips.org Cc: Imre Kaloz <kaloz@openwrt.org> Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1960/Signed-off-by:
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Gabor Juhos authored
Almost all boards have one or more push buttons connected to GPIO lines. This patch adds common code to register a platform_device for them. The patch also adds support for the buttons on the PB44 board. Signed-off-by:
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Gabor Juhos authored
All supported SoCs have a built-in hardware watchdog driver. This patch registers a platform_device for that to make it usable. Signed-off-by:
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Gabor Juhos authored
Almost all boards have one or more LEDs connected to GPIO lines. This patch adds common code to register a platform_device for them. The patch also adds support for the LEDs on the PB44 board. Signed-off-by:
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Gabor Juhos authored
Signed-off-by:
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Gabor Juhos authored
Signed-off-by:
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Gabor Juhos authored
This patch implements generic GPIO routines for the built-in GPIO controllers of the Atheros AR71XX/AR724X/AR913X SoCs. Signed-off-by:
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Gabor Juhos authored
This patch adds initial support for various Atheros SoCs based on the MIPS 24Kc core. The following models are supported at the moment: - AR7130 - AR7141 - AR7161 - AR9130 - AR9132 - AR7240 - AR7241 - AR7242 The current patch contains minimal support only, but the resulting kernel can boot into user-space with using of an initramfs image on various boards which are using these SoCs. Support for more built-in devices and individual boards will be implemented in further patches. Signed-off-by:
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David Daney authored
In order not to be left behind, we add jump label support for MIPS. Tested on 64-bit big endian (Octeon), and 32-bit little endian (malta/qemu). Signed-off-by:
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David Daney authored
On the off chance that uasm ever warns about overflow, there is no way to know what the offending instruction is. Change the printks to WARNs, so we can get a nice stack trace. It has the added benefit of being much more noticeable than the short single line warning message, so is less likely to be ignored. Signed-off-by:
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David Daney authored
Octeon can use scratch registers in the TLB handlers. Octeon II can use LDX instructions. Signed-off-by:
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David Daney authored
Needed by Octeon II optimized TLB handlers. Signed-off-by:
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David Daney authored
If the CPU supports BBIT0 and BBIT1, use them in TLB handlers as they are more efficient than an AND followed by an branch and then restoring the clobbered register. Signed-off-by:
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David Daney authored
these are already defined, but declaring them allow them to be used outside of uasm.c. Signed-off-by:
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David Daney authored
Decide at runtime to use either Context or KScratch to hold the PGD pointer. Signed-off-by:
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David Daney authored
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David Daney authored
Probe c0_config4 for KScratch registers and report them in /proc/cpuinfo. Signed-off-by:
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Gabor Juhos authored
This patch adds a generic solution to support multiple machines based on a given SoC within a single kernel image. It is implemented already for several other architectures but MIPS has no generic support for that yet. [Ralf: This competes with DT but DT is a much more complex solution and this code has been used by OpenWRT for a long time so for now DT is a bad reason to stop the merge but longer term this should be migrated to DT.] Signed-off-by:
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Joe Perches authored
Using %pR standardizes the struct resource output. Signed-off-by:
Joe Perches <joe@perches.com> To: Jiri Kosina <trivial@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1772/Signed-off-by:
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