- 30 May, 2014 35 commits
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Maciej W. Rozycki authored
Update to commit 9c9b415c [MIPS: Reimplement get_cycles().] On systems were for whatever reasons we can't use the cycle counter, fall back to the c0_random register as an entropy source. It has however a very small range that makes it suitable for random_get_entropy only and not get_cycles. This optimised version compiles to 8 instructions in the fast path even in the worst case of all the conditions to check being variable (including a MFC0 move delay slot that is only required for very old processors): 828: 8cf90000 lw t9,0(a3) 828: R_MIPS_LO16 jiffies 82c: 40057800 mfc0 a1,c0_prid 830: 3c0200ff lui v0,0xff 834: 00a21024 and v0,a1,v0 838: 1040007d beqz v0,a30 <add_interrupt_randomness+0x22c> 83c: 3c030000 lui v1,0x0 83c: R_MIPS_HI16 cpu_data 840: 40024800 mfc0 v0,c0_count 844: 00000000 nop 848: 00409021 move s2,v0 84c: 8ce20000 lw v0,0(a3) 84c: R_MIPS_LO16 jiffies On most targets the sequence will be shorter and on some it will reduce to a single `MFC0 <reg>,c0_count', as all MIPS architecture (i.e. non-legacy MIPS) processors require the CP0 Count register to be present. The only known exception that reports MIPS architecture compliance, but contrary to that lacks CP0 Count is the Ingenic JZ4740 thingy. For broken platforms like that this code requires cpu_has_counter to be hardcoded to 0 (i.e. no variable setting is permitted) so as not to penalise all the other good platforms out there. The asm barrier is required so that the compiler does not pull any potentially costly (cold cache!) `cpu_data' variable access into the fast path. Signed-off-by:
Ralf Baechle <ralf@linux-mips.org> Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: Theodore Ts'o <tytso@mit.edu> Cc: John Crispin <blogic@openwrt.org> Cc: Andrew McGregor <andrewmcgr@gmail.com> Cc: Dave Taht <dave.taht@bufferbloat.net> Cc: Felix Fietkau <nbd@nbd.name> Cc: Simon Kelley <simon@thekelleys.org.uk> Cc: Jim Gettys <jg@freedesktop.org> Cc: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6702/Signed-off-by:
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Ganesan Ramalingam authored
The XLP9XX SoC has an on-chip SATA controller with two ports. Add ahci-init-xlp2.c to initialize the controller, setup the glue logic registers, fixup PCI quirks and setup interrupt ack logic. Signed-off-by:
Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by:
Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6913/Signed-off-by:
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Ganesan Ramalingam authored
XLP3XX includes an on-chip SATA controller with 4 ports. The controller needs glue logic initialization and PCI fixup before it can be used with the standard AHCI driver. Signed-off-by:
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Ganesan Ramalingam authored
In XLP9XX, the interrupt routing table for MSI-X has been moved to the PCIe controller's config space from PIC. There are also 32 MSI-X interrupts available per link on XLP9XX. Update XLP MSI/MSI-X code to handle this. Signed-off-by:
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Yonghong Song authored
Add support for the XLP5XX processor which is an 8 core variant of the XLP9XX. Add XLP5XX cases to code which earlier handled XLP9XX. Signed-off-by:
Yonghong Song <ysong@broadcom.com> Signed-off-by:
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Jayachandran C authored
Calculate XLP 9XX and 2XX core frequency from the per-core PLL. This should give the correct value for all board configurations. Signed-off-by:
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Ganesan Ramalingam authored
Update PIC frequency calculation for XLP9XX and 2XX processors using the correct PLL registers. This should work for all possible board configurations. Signed-off-by:
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Jayachandran C authored
Add the compatible property to the PIC entry. Also fix up the nodename to use the correct address. Signed-off-by:
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Jayachandran C authored
Use PRID_IMP_MASK macro instead of 0xff00 to extract the processor type. Signed-off-by:
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Jayachandran C authored
Add IRQ to IRT (PIC interupt table index) mapping for SATA, GPIO, NAND and SPI interfaces on the XLP SoC. Fix offsets for few blocks and add device IDs for a few blocks. Signed-off-by:
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Jayachandran C authored
The ELPA bit needs to be set in the PAGEGRAIN register to enable access to >64GB physical address. Update reset.S to do this from every hardware thread. Signed-off-by:
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Jayachandran C authored
Update thread wakeup function to use scratch registers for saving SP and RA. Move the register restore code needed for thread 0 to the calling function. This reduces the size of code copied to the reset vector. Signed-off-by:
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Jayachandran C authored
Use standard function to print cpumask. Also fixup a typo in the same file. Signed-off-by:
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Jayachandran C authored
Warn and return if invalid IRQ is passed to nlm_set_pic_extra_ack. Signed-off-by:
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Jayachandran C authored
This is needed for nlm_node_present(0) to work on uniprocessor compile. Signed-off-by:
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Jayachandran C authored
The macros in topology.h need CONFIG_SMP, and the uniprocessor compilation fails due to this. Wrap the macros in an ifdef so that uniprocessor works. Signed-off-by:
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Jayachandran C authored
This is needed for two node XLP9xx configurations. Signed-off-by:
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Markos Chandras authored
Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6743/Signed-off-by:
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Markos Chandras authored
This adds initial support for BPF-JIT on MIPS Tested on mips32 LE/BE and mips64 BE/n64 using dhcp, ping and various tcpdump filters. Benchmarking: Assuming the remote MIPS target uses 192.168.154.181 as its IP address, and the local host uses 192.168.154.136, the following results can be obtained using the following tcpdump filter (catches no frames) and a simple 'time ping -f -c 1000000' command. [root@(none) ~]# tcpdump -p -n -s 0 -i eth0 net 10.0.0.0/24 -d (000) ldh [12] (001) jeq #0x800 jt 2 jf 8 (002) ld [26] (003) and #0xffffff00 (004) jeq #0xa000000 jt 16 jf 5 (005) ld [30] (006) and #0xffffff00 (007) jeq #0xa000000 jt 16 jf 17 (008) jeq #0x806 jt 10 jf 9 (009) jeq #0x8035 jt 10 jf 17 (010) ld [28] (011) and #0xffffff00 (012) jeq #0xa000000 jt 16 jf 13 (013) ld [38] (014) and #0xffffff00 (015) jeq #0xa000000 jt 16 jf 17 (016) ret #65535 - BPF-JIT Disabled real 1m38.005s user 0m1.510s sys 0m6.710s - BPF-JIT Enabled real 1m35.215s user 0m1.200s sys 0m4.140s [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: -
Markos Chandras authored
It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: -
Markos Chandras authored
It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: -
Markos Chandras authored
It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by:
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Markos Chandras authored
It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by:
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Markos Chandras authored
It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by:
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Markos Chandras authored
It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by:
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Markos Chandras authored
It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by:
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Markos Chandras authored
It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by:
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Markos Chandras authored
It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by:
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Markos Chandras authored
It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by:
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Markos Chandras authored
It will be used later on by bpf-jit [ralf@linux-mips.org: Fixed conflict due to other preceeding conflicts.] Signed-off-by:
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Markos Chandras authored
It will be used later on by bpf-jit [ralf@linux-mips.org: Fixed conflict with 49e9529b [MIPS: uasm: add jalr instruction]. Signed-off-by:
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Markos Chandras authored
It will be used later one for the jalr and wsbh instructions. [ralf@linux-mips.org: Dropped arch/mips/include/asm/uasm.h segment because that was already added by 49e9529b [MIPS: uasm: add jalr instruction]. Signed-off-by:
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Markos Chandras authored
It will be used later on by the sllv and srlv instructions. Signed-off-by:
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Deng-Cheng Zhu authored
Sometimes it's useful to let the user, while doing performance research, know what in the IEEE754 exceptions has caused many times of FP emulation when running a specific application. This patch adds 5 more files to /sys/kernel/debug/mips/fpuemustats/, whose filenames begin with "ieee754". These stats are in addition to the existing cp1ops, cp1xops, errors, loads and stores, which may not be useful in understanding the reasons of ieee754 exceptions. [ralf@linux-mips.org: Fixed reject due to other changes to the kernel FP assist software.] Signed-off-by:
Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven.Hill@imgtec.com Cc: james.hogan@imgtec.com Patchwork: http://patchwork.linux-mips.org/patch/7044/Signed-off-by:
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Rafał Miłecki authored
Patch was tested on devices with 64 MiB and 256 MiB of RAM. It documents every part nicely and drops this hacky part of code: max = off | ((128 << 20) - 1); Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/6808/Signed-off-by:
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- 29 May, 2014 2 commits
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Alex Smith authored
Add interface mode detection for Octeon II. This is necessary to detect the interface modes correctly on the UBNT E200 board. Code is taken from the UBNT GPL source release, with some alterations: SRIO, ILK and RXAUI interface modes are removed and instead return disabled as these modes are not currently supported. Signed-off-by:
Alex Smith <alex.smith@imgtec.com> Tested-by:
David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7039/Signed-off-by:
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- 28 May, 2014 3 commits
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Paul Burton authored
The CONFIG_MIPS_CPS SMP implementation should be able to handle all cases the CONFIG_MIPS_CMP implementation does, but without requiring bootloader assistance. It is also required in order to make use of features such as hotplug & cpuidle core power gating. Enable it by default for Malta configs that previously enabled the now deprecated CONFIG_MIPS_CMP, and disable the latter. The local version suffix "cmp" is removed rather than replaced with "cps" since there are other ways to tell that the CPS SMP implementation is in use (the "VPE topology" line in the boot log being one). Signed-off-by:Paul Burton <paul.burton@imgtec.com>
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Paul Burton authored
This patch adds a cpuidle driver for systems based around the MIPS Coherent Processing System (CPS) architecture. It supports four idle states: - The standard MIPS wait instruction. - The non-coherent wait, clock gated & power gated states exposed by the recently added pm-cps layer. The pm-cps layer is used to enter all the deep idle states. Since cores in the clock or power gated states cannot service interrupts, the gic_send_ipi_single function is modified to send a power up command for the appropriate core to the CPC in cases where the target CPU has marked itself potentially incoherent. Signed-off-by: -
Paul Burton authored
Declaring this allows drivers which need to initialise each struct cpuidle_device at initialisation time to make use of the structures already defined in cpuidle.c, rather than having to wastefully define their own. Signed-off-by:
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