- 19 Feb, 2022 3 commits
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Jonathan Marek authored
When egpio_enable bit is cleared, the gpio is driven by SSC/LPASS TLMM and the APSS TLMM settings are ignored. Reflect that in the debugfs dump. Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20220210131210.24605-2-jonathan@marek.caSigned-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Jonathan Marek authored
This mirrors egpio support added for sc7280. This change is necessary for gpios 165 to 209 to be driven by APSS. Signed-off-by:
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.18 - Add MOST (MediaLB I/F) pins on R-Car E3 and D3, - Add support for the new RZ/V2L SoC, - Miscellaneous fixes and improvements.
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- 11 Feb, 2022 12 commits
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Colin Ian King authored
There is a spelling mistake in the documentation. Fix it. Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Acked-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220202091551.580372-1-colin.i.king@gmail.comSigned-off-by:
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Jonathan Neuschäfer authored
The name "DS" is defined in arch/x86/um/shared/sysdep/ptrace_64.h, which results in a compiler warning when build-testing on ARCH=um. Rename this driver's "DS" macro to DSTR so avoid this collision. Reported-by:
kernel test robot <lkp@intel.com> Fixes: 3b588e43 ("pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver") Signed-off-by:
Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20220205155332.1308899-3-j.neuschaefer@gmx.netSigned-off-by:
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Jonathan Neuschäfer authored
When compile-testing on 64-bit architectures, GCC complains about the mismatch of types between the %d format specifier and value returned by ARRAY_LENGTH(). Use %zu, which is correct everywhere. Reported-by:
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kernel test robot authored
drivers/pinctrl/pinctrl-starfive.c:1029:2-3: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Reported-by:
Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/20220206003735.GA94316@d6598ff186c2Signed-off-by:
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Chen-Yu Tsai authored
When the constraints and description for bias-pull-{up,down} were added, the constraints were not indented correctly, resulting in them being parsed as part of the description. This effectively nullified their purpose. Move the constraints out of the description block, make each description part of the same associative array as the enum its describing, and reindent them correctly so they take effect. Also add "type: boolean" to the list of valid values. This corresponds to having bias-pull-{up,down} without any arguments. Fixes: 91e7edce ("dt-bindings: pinctrl: mt8195: change pull up/down description") Signed-off-by:Chen-Yu Tsai <wenst@chromium.org> Reviewed-by:
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Horatiu Vultur authored
The blamed commit adds support for irq, but the reqisters for irq are outside of the memory size. They are at address 0x108. Therefore update the memory size to cover all the registers used by the device. Fixes: 01a9350b ("dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add irq support") Signed-off-by:
Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20220204153535.465827-2-horatiu.vultur@microchip.comSigned-off-by:
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Kunihiko Hayashi authored
Add USB device pinmux settings for PXs2 and PXs3 SoCs. Only pins for ports 0 and 1 support USB device mode. Signed-off-by:
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1643376903-18623-4-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by:
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Kunihiko Hayashi authored
Current pinmux group for audio in/out assumes 4ch I2S case but the UniPhier AIO hardware also supports 1ch and 2ch I2S. So divide current ain1 group into ain1, ain1_dat2 and ain1_dat4 groups. Divide other ain and aout in the same way. Signed-off-by:
Ryuta NAKANISHI <nakanishi.ryuta@socionext.com> Signed-off-by:
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Kunihiko Hayashi authored
Add missing audio I/O pinmux settings for PXs2 SoC. This adds ain1 4ch pins, ain3 and aout1. Signed-off-by:
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Rayyan Ansari authored
The PM8226 provides 8 MPPs. Add a compatible to support them. Signed-off-by:
Rayyan Ansari <rayyan@ansari.sh> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220124171538.18088-2-rayyan@ansari.shSigned-off-by:
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Rayyan Ansari authored
Document the Device Tree binding for PM8226 MPPs. Signed-off-by:
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Luca Weiss authored
Allow the gpio-reserved-ranges property to be used in dts. Signed-off-by:
Luca Weiss <luca@z3ntu.xyz> Acked-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Acked-by:
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- 08 Feb, 2022 6 commits
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Biju Das authored
Update rzg2l_gpio_register() to use driver data for chip->names and check for gpio-range. This allows reusing the driver for SoC's with different port pin definitions(eg:- RZ/G2UL SoC has fewer ports compared to RZ/G2L and port pin definitions are different). Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220206194614.13209-2-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Geert Uytterhoeven authored
Move the msiof* pin groups where they belong. Signed-off-by:
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Geert Uytterhoeven authored
Move the du* pin function where it belongs. Signed-off-by:
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Geert Uytterhoeven authored
Move the sdhi* pin functions where they belong. Signed-off-by:
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Geert Uytterhoeven authored
Rename the MOD_SEL2_* definitions, to match the bitfield order in IPxSRy_* definitions and in MOD_SEL* definitions in other drivers. No changes in generated code. Signed-off-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/4880e4cbc112ee26569bf29a21c070125461e58d.1642524603.git.geert+renesas@glider.be
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Biju Das authored
RZ/V2L uses the RZ/G2L GPIO and pinctrl driver. Enable the RZ/G2L pinctrl driver if RZ/V2L is enabled. Update the description for RZ/V2L pin control support. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220110134659.30424-8-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/r/20220206194614.13209-1-biju.das.jz@bp.renesas.comSigned-off-by:
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- 02 Feb, 2022 2 commits
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Horatiu Vultur authored
This patch adds support for ServalT pinctrl, using the ocelot driver as basis. Signed-off-by:
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Horatiu Vultur authored
Add the documentation for the Microsemi ServalT pinmuxing and gpio controller. Signed-off-by:
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- 30 Jan, 2022 5 commits
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Wells Lu authored
Add driver for Sunplus SP7021 SoC. Signed-off-by:
Wells Lu <wellslutw@gmail.com> Link: https://lore.kernel.org/r/1642344734-27229-3-git-send-email-wellslutw@gmail.comSigned-off-by:
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Wells Lu authored
Add dt-bindings header files and documentation for Sunplus SP7021 SoC. Signed-off-by:
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Qianggui Song authored
Add new pinctrl driver for Amlogic's Meson-S4 SoC which share the same register layout as the previous Meson-A1. Acked-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
Qianggui Song <qianggui.song@amlogic.com> Link: https://lore.kernel.org/r/20220113031044.2665-4-qianggui.song@amlogic.comSigned-off-by:
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Qianggui Song authored
Add a new dt-binding header file which documents the detail pin names. Reviewed-by:
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Qianggui Song authored
Add new compatible for Amlogic's Meson-S4 pin controller Reviewed-by:
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- 25 Jan, 2022 2 commits
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Rafał Miłecki authored
BCM4908 has its own pins layout so it needs a custom binding and a Linux driver. Signed-off-by:
Rafał Miłecki <rafal@milecki.pl> Reviewed-by:
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Rafał Miłecki authored
It's hardware block that is part of every SoC from BCM4908 family. Signed-off-by:
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- 24 Jan, 2022 10 commits
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Biju Das authored
Document Renesas RZ/V2L pinctrl bindings. The RZ/V2L SoC is package- and pin-compatible with RZ/G2L. No driver changes are required as the RZ/G2L compatible string "renesas,r9a07g044-pinctrl" will be used as a fallback. Signed-off-by:
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Nikita Yushchenko authored
This adds pins, groups, and functions for MediaLB devices on Renesas R-Car E3 and D3 SoCs. Signed-off-by:
Nikita Yushchenko <nikita.yoush@cogentembedded.com> Link: https://lore.kernel.org/r/20211225191713.2187975-1-nikita.yoush@cogentembedded.comSigned-off-by:
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Geert Uytterhoeven authored
The INTC_IRQx_N pin functions were only documented in preliminary versions of the R-Car M2 Hardware User's Manual, and were never used. This reduces kernel size by 40 bytes. Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/932834b388887e1ae267e5a852c688c79091a5f9.1640269369.git.geert+renesas@glider.be
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Geert Uytterhoeven authored
The INTC_IRQx_N pin functions were only documented in preliminary versions of the R-Car H2 Hardware User's Manual, and were never used. This reduces kernel size by 40 bytes. Signed-off-by:
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Lad Prabhakar authored
Add description for "power-source" property mentioning the values in enum are in millivolt. Suggested-by:
Pavel Machek <pavel@denx.de> Signed-off-by:
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Wolfram Sang authored
For Renesas PFCs not setting .strict, we can snoop GPIOs which are already muxed to some other function. To actually make use of that, we shouldn't mux them back to GPIO if they have been already muxed to something. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20211210113226.40111-1-wsa+renesas@sang-engineering.comSigned-off-by:
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Lad Prabhakar authored
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypasses the hierarchical setup and messes up the irq chaining. In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq(). While at it, replace the dev_err() with dev_dbg() as platform_get_irq() prints an error message upon error. Signed-off-by:
Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by:
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Manivannan Sadhasivam authored
The MSM GPIO IRQ controller relies on the parent IRQ controller to set the CPU affinity for the IRQ. And this is only valid if there is any wakeup parent available and defined in DT. For the case of no parent IRQ controller defined in DT, msm_gpio_irq_set_affinity() and msm_gpio_irq_set_vcpu_affinity() should return -EINVAL instead of 0 as the affinity can't be set. Otherwise, below warning will be printed by genirq: genirq: irq_chip msmgpio did not update eff. affinity mask of irq 70 Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20220113162617.131697-1-manivannan.sadhasivam@linaro.orgSigned-off-by:
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Gary Bisson authored
Add missing PWM_F pin muxing for GPIOA_11 and GPIOZ_12. Signed-off-by:
Gary Bisson <gary.bisson@boundarydevices.com> Reviewed-by:
Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220112211642.2248901-2-gary.bisson@boundarydevices.comSigned-off-by:
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Douglas Anderson authored
If the drive-strength isn't specified in the device tree then it doesn't actually default to 2. Instead, it defaults to whatever the heck the BIOS left it at. If the BIOS doesn't touch it then that means it's whatever the heck the initial state of the pin was when the SoC booted. Reported-by:
Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
Douglas Anderson <dianders@chromium.org> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20220111140519.1.Ie2662d6289af1e9758b14b37149703c846d5f509@changeidSigned-off-by:
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