- 20 Nov, 2012 1 commit
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David Herrmann authored
We link every DRM "file_priv" to a "drm_master" structure. Currently, the drmSetMaster() call returns 0 when there is _any_ active master associated with the "drm_master" structure of the calling "file_priv". This means, that after drmSetMaster() we are not guaranteed to be DRM-Master and might not be able to perform mode-setting. A way to reproduce this is by starting weston with the DRM backend from within an X-console (eg., xterm). Because the xserver's "drm_master" is currently active, weston is assigned to the same master but is inactive because its VT is inactive and the xserver is still active. But when "fake-activating" weston, it calls drmSetMaster(). With current behavior this returns "0/success" and weston thinks that it is DRM-Master, even though it is not (as the xserver is still DRM-Master). Expected behavior would be drmSetMaster() to return -EINVAL, because the xserver is still DRM-Master. This patch changes exactly that. The only way this bogus behavior would be useful is for clients to check whether their associated "drm_master" is currently the active DRM-Master. But this logic fails if no DRM-Master is currently active at all. Because then the client itself would become DRM-Master (if it is root) and this makes this whole thing useles. Also note that the second "if-condition": file_priv->minor->master != file_priv->master is always true and can be skipped. Signed-off-by:
David Herrmann <dh.herrmann@googlemail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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- 19 Nov, 2012 1 commit
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git://people.freedesktop.org/~danvet/drm-intelDave Airlie authored
Daniel writes: Highlights of this -next round: - ivb fdi B/C fixes - hsw sprite/plane offset fixes from Damien - unified dp/hdmi encoder for hsw, finally external dp support on hsw (Paulo) - kill-agp and some other prep work in the gtt code from Ben - some fb handling fixes from Ville - massive pile of patches to align hsw VGA with the spec and make it actually work (Paulo) - pile of workarounds from Jesse, mostly for vlv, but also some other related platforms - start of a dev_priv reorg, that thing grew out of bounds and chaotic - small bits&pieces all over the place, down to better error handling for load-detect on gen2 (Chris, Jani, Mika, Zhenyu, ...) On top of the previous pile (just copypasta): - tons of hsw dp prep patches form Paulo - round scheduled work items and timers to nearest second (Chris) - some hw workarounds (Jesse&Damien) - vlv dp support and related fixups (Vijay et al.) - basic haswell dp support, not yet wired up for external ports (Paulo) - edp support (Paulo) - tons of refactorings to prepare for the above (Paulo) - panel rework, unifiying code between lvds and edp panels (Jani) - panel fitter scaling modes (Jani + Yuly Novikov) - panel power improvements, should now work without the BIOS setting it up - extracting some dp helpers from radeon/i915 and move them to drm_dp_helper.c - randome pile of workarounds (Damien, Ben, ...) - some cleanups for the register restore code for suspend/resume - secure batchbuffer support, should enable tear-free blits on gen6+ Chris) - random smaller fixlets and cleanups. * 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel: (231 commits) drm/i915: Restore physical HWS_PGA after resume drm/i915: Report amount of usable graphics memory in MiB drm/i915/i2c: Track users of GMBUS force-bit drm/i915: Allocate the proper size for contexts. drm/i915: Update load-detect failure paths for modeset-rework drm/i915: Clear unused fields of mode for framebuffer creation drm/i915: Always calculate 8xx WM values based on a 32-bpp framebuffer drm/i915: Fix sparse warnings in from AGP kill code drm/i915: Missed lock change with rps lock drm/i915: Move the remaining gtt code drm/i915: flush system agent TLBs on SNB drm/i915: Kill off now unused gen6+ AGP code drm/i915: Calculate correct stolen size for GEN7+ drm/i915: Stop using AGP layer for GEN6+ drm/i915: drop the double-OP_STOREDW usage in blt_ring_flush drm/i915: don't rewrite the GTT on resume v4 drm/i915: protect RPS/RC6 related accesses (including PCU) with a new mutex drm/i915: put ring frequency and turbo setup into a work queue v5 drm/i915: don't block resume on fb console resume v2 drm/i915: extract l3_parity substruct from dev_priv ...
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- 16 Nov, 2012 1 commit
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Chris Wilson authored
By always setting up the HWS register for both physical and virtual address variations during render ring we can reduce the number of different special cases that get set up at varying different times during module load. Fixes regression from commit c630119f Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Wed Oct 17 11:32:57 2012 +0200 drm/i915: don't save/restore HWS_PGA reg for kms Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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- 13 Nov, 2012 2 commits
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Chris Wilson authored
...rather than kilo-PTE. Signed-off-by:
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Chris Wilson authored
This fixes a regression for SDVO from commit fbfcc4f3 Author: Jani Nikula <jani.nikula@intel.com> Date: Mon Oct 22 16:12:18 2012 +0300 drm/i915/sdvo: restore i2c adapter config on intel_sdvo_init() failures As SDVOB and SDVOC are multiplexed on the same pin, if a chipset does not have the second SDVO encoder, it will then remove the force-bit setting on the common i2c adapter during teardown. All subsequent attempts of trying to use GMBUS with SDVOB then fail. Signed-off-by:
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- 11 Nov, 2012 35 commits
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Ben Widawsky authored
Whoops. This was fixed previously, but not sure how it got lost. It's not needed for -fixes or stable because at the moment drm_i915_file_private is way bigger than i915_hw_context (by 120 bytes on my 64b build). Signed-off-by:
Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
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Chris Wilson authored
After the rework, intel_set_mode() became a little better behaved in restoring the current mode if we failed to apply the requested modeline. However, the failure path for load-detect would clobber the existing state, leading to an oops during BIOS takeover on older machines. Signed-off-by:
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Chris Wilson authored
With the stricter checks introduced in commit ac911edae5960d7dccd9883f5fa5d25b591520de Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Wed Oct 31 17:50:19 2012 +0200 drm/i915: Check the framebuffer offset (and friends), it became especially prudent to make sure that the additional fields inside the mode were cleared before attempting to create a framebuffer. In particular, the fb created for load detection failed to do so and hence failed. Signed-off-by:Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Chris Wilson authored
The specs for gen2 say that the watermark values "should always be set assuming a 32bpp display mode, even though the display mode may be 15 or 16 bpp." Signed-off-by:
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Ben Widawsky authored
Reported-by:
Fengguang Wu <fengguang.wu@intel.com> Signed-off-by:
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Ben Widawsky authored
Fixes a WARN_ON in igt/tests/debugfs_reader CC: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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Ben Widawsky authored
It's pretty much all consolidated now that we've killed AGP. We can move the one outlier, and defines too. (Kill some unused defines in the process) Signed-off-by:
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Ben Widawsky authored
This allows us to map the PTEs WC. I've not done thorough testing or performance measurements with this patch, but it should be decent. This is based on a patch from Jesse with the original commit message > I've only lightly tested this so far, but the corruption seems to be > gone if I write the GFX_FLSH_CNTL reg after binding an object. This > register should control the TLB for the system agent, which is what CPU > mapped objects will go through. It has been updated for the new AGP-less code by me, and included with it is feedback from the original patch. v2: Updated to reflect paranoia on pte updates/register posting reads. Signed-off-by:
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Ben Widawsky authored
v2: Accidently removed an ILK case in i9xx_setup (Nicely found by Chris) CC: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by [v1] : Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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Ben Widawsky authored
This bug existed in the old code, but was easier to fix here in the rework. Unfortunately gen7 doesn't have a nice way to figure out the size and we must use a lookup table. As Jesse pointed out, there is some confusion in the docs about these definitions. We're picking the one which seems more accurate, but we really aren't certain. Signed-off-by:
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Ben Widawsky authored
As a quick hack we make the old intel_gtt structure mutable so we can fool a bunch of the existing code which depends on elements in that data structure. We can/should try to remove this in a subsequent patch. This should preserve the old gtt init behavior which upon writing these patches seems incorrect. The next patch will fix these things. The one exception is VLV which doesn't have the preserved flush control write behavior. Since we want to do that for all GEN6+ stuff, we'll handle that in a later patch. Mainstream VLV support doesn't actually exist yet anyway. v2: Update the comment to remove the "voodoo" Check that the last pte written matches what we readback v3: actually kill cache_level_to_agp_type since most of the flags will disappear in an upcoming patch v4: v3 was actually not what we wanted (Daniel) Make the ggtt bind assertions better and stricter (Chris) Fix some uncaught errors at gtt init (Chris) Some other random stuff that Chris wanted v5: check for i==0 in gen6_ggtt_bind_object to shut up gcc (Ben) Signed-off-by:
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Daniel Vetter authored
This has been introduced in "drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op". Reported-by:
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Jesse Barnes authored
The BIOS shouldn't be touching this memory across suspend/resume, so just leave it alone. This saves us ~6ms on resume on my T420 (retested with write combined PTEs). v2: change gtt restore default on pre-gen4 (Chris) move needs_gtt_restore flag into dev_priv v3: make sure we restore GTT on resume from hibernate (Daniel) use opregion support as the cutoff for restore from resume (Chris) v4: use a better check for opregion (Chris) Reviewed-by:Jesse Barnes <jbarnes@virtuousgeek.org> [danvet: Kill the needs_gtt_restore indirection and check directly for OpRegion. Also explain in a comment what's going on.] Signed-off-by:
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Jesse Barnes authored
This allows the power related code to run independently of the rest of the pipeline, extending the resume and init time improvements into userspace, which would otherwise have been blocked on the struct mutex if we were doing PCU communication. v2: Also convert the locking for the rps sysfs interface. Suggested-by:
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Jesse Barnes authored
Communicating via the mailbox registers with the PCU can take quite awhile. And updating the ring frequency or enabling turbo is not something that needs to happen synchronously, so take it out of our init and resume paths to speed things up (~200ms on my T420). v2: add comment about why we use a work queue (Daniel) make sure work queue is idle on suspend (Daniel) use a delayed work queue since there's no hurry (Daniel) v3: make cleanup symmetric and just call cancel work directly (Daniel) v4: schedule the work using round_jiffies_up to batch work better (Chris) v5: fix the right schedule_delayed_work call (Chris) References: https://bugs.freedesktop.org/show_bug.cgi?id=54089Signed-of-by:Jesse Barnes <jbarnes@virtuougseek.org> [danvet: bikeshed the placement of the new delayed work, move it to all the other gen6 power mgmt stuff.] Signed-off-by:
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Jesse Barnes authored
The console lock can be contended, so rather than prevent other drivers after us from being held up, queue the console suspend into the global work queue that can happen anytime. I've measured this to take around 200ms on my T420. Combined with the ring freq/turbo change, we should save almost 1/2 a second on resume. v2: use console_trylock() to try to resume the console immediately (Chris) Signed-off-by:
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Daniel Vetter authored
Pretty astonishing how far apart these two members landed ... Especially since I've already removed almost 200 lines in between. Reviewed-by:
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Daniel Vetter authored
Also, move dev_priv->counter there, it's only used in i915_dma.c And also move the dri1 dungeon at the end of dev_priv where no one cares about it. Reviewed-by:
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Daniel Vetter authored
Reviewed-by:
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Daniel Vetter authored
And give the structs slightly more generic names. I've decided to keep the short rps/ips prefix, since that's just easier and less churn. Reviewed-by:
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Daniel Vetter authored
dev_priv has grown way too big, and grouping memebers into substructs and moving them out of line helps re-gain some overview. Unfortunatley I couldn't just call the substruct save and drop the prefix, since that will make most member names clash with registers #defines. Changes in i915_drv.h done by hand, everything else changed with s/\<save\([A-Z]*\)/regfile.save\1/ in vim. Reviewed-by:
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Jesse Barnes authored
So we can write them properly. Signed-off-by:
Antti Koskipää <antti.koskipaa@intel.com> Signed-off-by:
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Jesse Barnes authored
"If ENABLED, PIPE_CONTROL command will flush the in flight data written out by render engine to Global Observation point on flush done. Also Requires stall bit ([20] of DW1) set." So set the stall bit to ensure proper invalidation. Signed-off-by:
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Jesse Barnes authored
So store into the scratch space of the HWS to make sure the invalidate occurs. v2: use GTT address space for store, clean up #defines (Chris) v3: use correct #define in blt ring flush (Chris) Signed-off-by:
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Jesse Barnes authored
Workaround for dual port PS dispatch on GT1. v2: pull in register definition & offset handling v3: use IVB GT1 macro to get the right regs (Ben) v4: add for VLV too (Ben) v5: don't read the reg, it's masked so we'll only enable the one extra bit (Chris) v6: use a _GT2 suffix for the second reg (Chris) Signed-off-by:
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Jesse Barnes authored
This allows us to get the right vblank interrupt frequency. v2: pull in register definition Signed-off-by:
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Jesse Barnes authored
References: https://bugs.freedesktop.org/show_bug.cgi?id=50250Reviewed-by:
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Jesse Barnes authored
v2: use correct register v3: remove extra hunks, pull in register definitions & offset check directly v4: add GT1 vs GT2 distinction for IVB portion (Ben) References: https://bugs.freedesktop.org/show_bug.cgi?id=50233Reviewed-by:
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Jesse Barnes authored
Needs to be set on every context restore as well, so set it as part of the initial state so we can save/restore it. Note this removes the IVB workaround value from VLV and uses the default value, just adding in the L3 cache aging disable bit, since the IVB value is wrong for VLV. Signed-off-by:
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Paulo Zanoni authored
This covers the "Disable FDI" section from the CRT mode set sequence. This disables the FDI receiver and also the FDI pll. Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
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Paulo Zanoni authored
This commit makes hsw_fdi_link_train responsible for implementing everything described in the "Enable and train FDI" section from the Hawell CRT mode set sequence documentation. We completely rewrite hsw_fdi_link_train to match the documentation and we also call it in the right place. This patch was initially sent as a series of tiny patches fixing every little problem of the function, but since there were too many patches fixing the same function it got a little difficult to get the "big picture" of how the function would be in the end, so here we amended all the patches into a single big patch fixing the whole function. Problems we fixed: 1 - Train Haswell FDI at the right time. We need to train the FDI before enabling the pipes and planes, so we're moving the call from lpt_pch_enable to haswell_crtc_enable directly. We are also removing ironlake_fdi_pll_enable since the PLL enablement on Haswell is completely different and is also done during the link training steps. 2 - Use the right FDI_RX_CTL register on Haswell There is only one PCH transcoder, so it's always _FDI_RXA_CTL. Using "pipe" here is wrong. 3 - Don't rely on DDI_BUF_CTL previous values Just set the bits we want, everything else is zero. Also POSTING_READ the register before sleeping. 4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train According to the mode set sequence documentation, this is the right place. According to the FDI_RX_TUSIZE register description, this is the value we should set. Also remove the code that sets this register from the old location: lpt_pch_enable. 5 - Properly program FDI_RX_MISC pwrdn lane values on HSW 6 - Wait only 35us for the FDI link training First we wait 30us for the FDI receiver lane calibration, then we wait 5us for the FDI auto training time. 7 - Remove an useless indentation level on hsw_fdi_link_train We already "break" when the link training succeeds. 8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE When we fail the training. 9 - Change Haswell FDI link training error messages We shouldn't call DRM_ERROR when still looping through voltage levels since this is expected and not really a failure. So in this commit we adjust the error path to only DRM_ERROR when we really fail after trying everything. While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since it's what we use everywhere. 10 - Try each voltage twice at hsw_fdi_link_train Now with Daniel Vetter's suggestion to use "/2" instead of ">>1". Signed-off-by: -
Jani Nikula authored
Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Paulo Zanoni authored
We had 2 places using X2 and one place using X1. Signed-off-by:
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Daniel Vetter authored
Now that we no longer pretend to have flexibility in matching any north display block with any pch, we can ditch this. v2: Fix the embarassing rebase fail that Paulo Zanoni spotted. Reviewed-by:
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Daniel Vetter authored
Found in Bspec vol4h South Display Engine Registers [CPT, PPT], section "5.3.1 TRANS_CHICKEN_1—Transcoder Chicken Bits 1" v2: Make it compile. Reviewed-by:
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