- 08 Oct, 2021 4 commits
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Wayne Lin authored
[Why & How] Got Werror when building with Clang-13: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dpia.c:195:2: error: variable 'ts' is used uninitialized whenever switch default is taken [-Werror,-Wsometimes-uninitialized] default: ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dpia.c:200:9: note: uninitialized use occurs here return ts; ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dpia.c:180:2: note: variable 'ts' is declared here enum dpia_set_config_ts ts; ^ 1 error generated. Fix it. Reported-by:Mike Lothian <mike@fireburn.co.uk> Signed-off-by:
Wayne Lin <Wayne.Lin@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Alex Deucher authored
Missing 4.1.2. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Colin Ian King authored
The variable result is being initialized with a value that is never read, it is being updated immediately afterwards in both branches of an if statement. The assignment is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Alex Deucher authored
Was missed when converting the driver over to IP based initialization. Tested-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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- 07 Oct, 2021 1 commit
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Nirmoy Das authored
Unify BO evicting functionality for possible memory types in amdgpu_ttm.c. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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- 06 Oct, 2021 35 commits
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Solomon Chiu authored
[Why] For those video format with 60 fps, the user space player could ask for 120Hz for playback. [How] Add 120 in the table of common rates. Signed-off-by:
Solomon Chiu <solomon.chiu@amd.com> Signed-off-by:
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Mukul Joshi authored
On Aldebaran, GPU driver will handle bad page retirement for GPU memory even though UMC is host managed. As a result, register a bad page retirement handler on the mce notifier chain to retire bad pages on Aldebaran. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by:
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Mukul Joshi authored
Export smca_get_bank_type for use in the AMD GPU driver to determine MCA bank while handling correctable and uncorrectable errors in GPU UMC. Signed-off-by:
Borislav Petkov <bp@suse.de> Signed-off-by:
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Nirmoy Das authored
Check first if debugfs is initialized before creating amdgpu debugfs files. References: https://gitlab.freedesktop.org/drm/amd/-/issues/1686Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Jude Shih authored
[Why] YELLOW_CARP_B0 address was not correct [How] Set YELLOW_CARP_B0 to 0x1A. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Jude Shih <shenshih@amd.com> Signed-off-by:
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Jude Shih authored
[Why] Condition variable sometimes terminated unexpectedly [How] Use wait_for_completion_timeout to avoid unexpected termination of CV Reviewed-by:
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Jude Shih authored
[why] 1. HPD callback function has deadlock problem 2. HPD status is not assigned 3. There is crash due to null pointer 4. link_enc is NULL in DPIA case [How] 1. Fix deadlock problem by moving it out of the drm_modeset_lock 2. Assign HPD status from the notify of outbox from dmub FW 3. Fix the crash by checking if pin or enc exists 4. Use link_enc_cfg_get_link_enc_used_by_link to dynamically assign Reviewed-by:
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Meenakshikumar Somasundaram authored
[Why & How] 1. Remove unnecessary dummy interrupt source for USB4 HPD & HPD RX 2. Adjust parameter for DPCD writing of link training process of DPIA link 3. Adjust specific AUX defer delay for DPIA link Reviewed-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Acked-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by:
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Jimmy Kizito authored
[Why & How] Additional debug flags that can be useful for testing USB4 DP link training. Add flags: - 0x2 : Forces USB4 DP link to non-LTTPR mode - 0x4 : Extends status read intervals to about 60s. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Jimmy Kizito authored
[Why] DIB_BE_CNTL<i>.DIG_HPD_SELECT selects the HPD block being used by the display endpoint assigned to DIG<i>. In the case of USB4 display endpoints, no physical HPD block is assigned. [How] Setting DIB_BE_CNTL<i>.DIG_HPD_SELECT to 5 indicates that no HPD is assigned to a display endpoint. Firmware decrements the HPD_SELECT value by 1 before writing it to the register. Reviewed-by:
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Jude Shih authored
[Why] To process SET_CONFIG transactions with DMUB using inbox1 and outbox1 mail boxes. [How] 1) DMUB posts SET_CONFIG reply as an Outbox1 message of type DMUB_OUT_CMD__SET_CONFIG_REPLY. 2) The dmub async to sync mechanism for AUX is modified to accommodate SET_CONFIG commands for both command issue and reply code paths. Reviewed-by:
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Meenakshikumar Somasundaram authored
[Why & How] To add support for dpia debug options. Reviewed-by:
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Jimmy Kizito authored
[Why] We requires information from DPCD in order to identify USB4 DP tunneling targets. [How] Add USB4 DP tunneling fields to DPCD struct and populate these fields during sink detection. Reviewed-by:
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Meenakshikumar Somasundaram authored
[Why] To process SET_CONFIG transactions with DMUB using inbox1 and outbox1 mail boxes. [How] 1) Added inbox1 DPIA command subtype DMUB_CMD__DPIA_SET_CONFIG_ACCESS to issue SET_CONFIG command to DMUB in dc_process_dmub_set_config_async(). DMUB processes the command with DPIA sends reply back immediately or in an outbox1 message triggering an outbox1 interrupt to driver. 2) DMUB posts SET_CONFIG reply as an Outbox1 message of type DMUB_OUT_CMD__SET_CONFIG_REPLY. 3) The dmub async to sync mechanism for AUX is modified to accommodate SET_CONFIG commands for both command issue and reply code paths. Reviewed-by:
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Jimmy Kizito authored
[Why & How] Clear training pattern sequence for hop in display path once clock recovery and equalization phases of DP tunnel link training completed. Reviewed-by:
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Jimmy Kizito authored
[Why] Equalisation is the mandatory second phase of DisplayPort link training over a USB4 DP tunnel. [How] Implement equalisation phase for DP tunneled over USB4 in DPIA training module. Reviewed-by:
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Jimmy Kizito authored
[Why] Clock recovery is the mandatory first phase of DP link training. [How] - Implement clock recovery phase in DPIA training module. - Add helper functions for building SET_CONFIG messages. Reviewed-by:
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Jimmy Kizito authored
[Why] Training settings need to be applied to DPIA link at start of each training loop. Note: FEC readiness should be configured before link training while FEC enablement should be configured once training is complete. [How] - Implement DPIA link configuration function. - Account for dynamically assigned link encoders during link configuration. Reviewed-by:
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Jimmy Kizito authored
[Why] Training of DPIA link differs enough from that of conventional DP link to warrant a separate implementation. [How] - Implement top-level of DPIA training loop. - Make functions shared between DP and DPIA link training "public". Reviewed-by:
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Jimmy Kizito authored
[Why & How] Conventional links are trained with fallback during sink detection. Have DPIA links trained with fallback too. Reviewed-by:
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Jimmy Kizito authored
[why & how] Driver does not need to train the first hop. Reviewed-by:
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Jimmy Kizito authored
[why & how] 1. Add stub for getting tunneling device data 2. Add check for phy_repeater_cnt < 0xff to LTTPR check 3. Add two more bits of information to DPIA links Reviewed-by:
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Jimmy Kizito authored
[why & how] Add stub for DPIA link training and define new DPIA DMUB commands to support it. Reviewed-by:
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Jimmy Kizito authored
[why & how] We will need a way to distinguish physically connected links and DPIA endpoints. Reviewed-by:
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Meenakshikumar Somasundaram authored
[WHY] To add support for HPD & HPD RX interrupt handling for USB4 DPIA in YELLOW_CARP_B0. USB4 DPIA HPD & HPD RX interrupts are issued from DMUB to driver as a outbox1 message. [HOW] 1) Created get_link_index_from_dpia_port_index() to retrieve link index from dpia port index for HPD & HPD RX dmub notifications. 2) Added DMUB HPD & HPD RX handling in dmub_srv_stat_get_notification(). Reviewed-by:
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Meenakshikumar Somasundaram authored
[WHY] To enable dc links for USB4 DPIA ports and AUX command tunneling for YELLOW_CARP_B0. [HOW] 1) Created dc links for all USB4 DPIA ports in create_links(). dc_link_construct() implementation is split for legacy DDC and DPIAs. As usb4 has no ddc, ddc->ddc_pin will be set to NULL for its dc link and this parameter will be used to identify the dc links as DPIA. The dc link for DPIA is further to be enhanced with implementation for link encoder and link initialization. 2) usb4_dpia_count in struct resource_pool will be initialized to 4 in dcn31_resource_construct() if the DCN is YELLOW_CARP_B0. 3) Enabled DMUB AUX via outbox for YELLOW_CARP_B0. Reviewed-by:
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Jimmy Kizito authored
[Why & How] USB4 endpoints are dynamically mapped. We create additional link encoders for USB4 use when DC is created and destroy them when DC is destructed Reviewed-by:
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Marek Olšák authored
ind_block_64b_no_128bcl means INDEP_64B && INDEP_128B && MAX_COMPRESSED_BLOCK_SIZE == 64B. Only used by gfx10.3. ind_block_64b means INDEP_64B && !INDEP_128B && MAX_COMPRESSED_BLOCK_SIZE == 64B. Only used by gfx9 and gfx10. Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Acked-by:
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Leo (Hanghong) Ma authored
[Why] During DQE's promotion test, error appears in dmesg at boot on dcn3.1; [How] Add NULL pointor check for the pointor to the amdgpu_dm_connector; Reviewed-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by:
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Jimmy Kizito authored
[Why] Trying to enable multiple displays simultaneously exposed shortcomings with the algorithm for dynamic link encoder assignment. The main problems were: - Assuming stream order remained constant across states would sometimes lead to invalid DIG encoder assignment. - Incorrect logic for deciding whether or not a DIG could support a stream would also sometimes lead to invalid DIG encoder assignment. - Changes in encoder assignment were wholesale while updating of the pipe backend is incremental. This would lead to the hardware state not matching the software state even with valid encoder assignments. [How] The following changes fix the identified problems. - Use stream pointer rather than stream index to track streams across states. - Fix DIG compatibility check by examining the link signal type rather than the stream signal type. - Modify assignment algorithm to make incremental updates so software and hardware states remain coherent. Additionally: - Add assertions and an encoder assignment validation function link_enc_cfg_validate() to detect potential problems with encoder assignment closer to their root cause. - Reduce the frequency with which the assignment algorithm is executed. It should not be necessary for fast state validation. Reviewed-by:
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Leo (Hanghong) Ma authored
[Why & How] The codes to blank all dp display have been called many times, so add a helper in dc_link to make it more concise. Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Aric Cyr authored
This version brings along following fixes: - New firmware version - Fix DMUB problems on stress test. - Improve link training by skip overrride for preferred link - Refinement of FPU code structure for DCN2 - Fix 3DLUT skipped programming - Fix detection of 4 lane for DPALT - Fix dcn3 failure due to dmcbu_abm not created - Limit display scaling to up to 4k for DCN 3.1 - Add helper for blanking all dp displays Acked-by:
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Anthony Koo authored
Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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Hansen authored
[Why] DPALT detection for B0 PHY has its own set of RDPCSPIPE registers [How] Use RDPCSPIPE registers to detect if DPALT lane is 4 lane Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Hansen <Hansen.Dsouza@amd.com> Signed-off-by:
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Nikola Cornij authored
[why] The existing limit was mistakenly bigger than 4k for DCN 3.1 Reviewed-by:
Zhan Liu <Zhan.Liu@amd.com> Acked-by:
Nikola Cornij <nikola.cornij@amd.com> Signed-off-by:
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