- 07 Nov, 2016 6 commits
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Takeshi Kihara authored
Correct HDMI parent clock so that the rate of the HDMI clock is 1/4 rather than 1/2 of the rate of PLL1 as per the v0.52 (Jun, 15) manual. Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Niklas Söderlund authored
Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by:
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Niklas Söderlund authored
Signed-off-by:
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Geert Uytterhoeven authored
Add r8a7743 and r8a7745 CPG Core Clock Definitions
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Sergei Shtylyov authored
Add macros usable by the device tree sources to reference the R8A7745 CPG clocks by index. The data comes from Table 7.2c in revision 1.00 of the RZ/G Series User's Manual. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
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Sergei Shtylyov authored
Add macros usable by the device tree sources to reference the R8A7743 CPG clocks by index. The data comes from Table 7.2b in revision 1.00 of the RZ/G Series User's Manual. Signed-off-by:
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- 02 Nov, 2016 29 commits
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Geert Uytterhoeven authored
soc: renesas: Add R-Car RST driver for obtaining mode pin state
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Geert Uytterhoeven authored
The R-Car Gen2 board code no longer calls rcar_gen2_clocks_init(). Signed-off-by:
Dirk Behme <dirk.behme@de.bosch.com>
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Geert Uytterhoeven authored
The R-Car H1 board code no longer calls r8a7779_clocks_init(). Signed-off-by:
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Geert Uytterhoeven authored
The R-Car M1A board code no longer calls r8a7778_clocks_init(). Signed-off-by:
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Geert Uytterhoeven authored
Now the R-Car Gen2 CPG clock driver obtains the state of the mode pins from the R-Car RST driver, there's no longer a need to pass this state explicitly. Hence we can just call of_clk_init() instead. Signed-off-by:
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Geert Uytterhoeven authored
Now the R-Car H1 CPG clock driver obtains the state of the mode pins from the R-Car RST driver, there's no longer a need to pass this state explicitly. Hence we can just remove the .init_time() callback, the generic ARM code will take care of calling of_clk_init() and clocksource_probe(). Signed-off-by:
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Geert Uytterhoeven authored
Now the R-Car M1A CPG clock driver obtains the state of the mode pins from the R-Car RST driver, there's no longer a need to pass this state explicitly. Hence we can just remove the .init_time() callback, the generic ARM code will take care of calling of_clk_init(). Signed-off-by:
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Geert Uytterhoeven authored
All R-Car Gen3 clock drivers now obtain the values of the mode pins from the R-Car RST driver. Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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Geert Uytterhoeven authored
Obtain the values of the mode pins from the R-Car RST driver, which relies on the presence in DT of a device node for the RST module. Signed-off-by:
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Geert Uytterhoeven authored
Obtain the values of the mode pins from the R-Car RST driver, which relies on the presence in DT of a device node for the RST module. Signed-off-by:
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Geert Uytterhoeven authored
Obtain the values of the mode pins from the R-Car RST driver, which relies on the presence in DT of a device node for the RST module. Fall back to our own private copy of rcar_gen2_read_mode_pins() for backward-compatibility with old DTs. Signed-off-by:
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Geert Uytterhoeven authored
Obtain the values of the mode pins from the R-Car RST driver, which relies on the presence in DT of a device node for the RESET/WDT module. Signed-off-by:
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Geert Uytterhoeven authored
Obtain the values of the mode pins from the R-Car RST driver, which relies on the presence in DT of a device node for the RESET/WDT module. Signed-off-by:
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Geert Uytterhoeven authored
Add a device node for the RST module, which provides a.o. reset control and mode pin monitoring. Signed-off-by:
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Geert Uytterhoeven authored
Add a device node for the RST module, which provides a.o. reset control and mode pin monitoring. Signed-off-by:
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Geert Uytterhoeven authored
Add a device node for the RST module, which provides a.o. reset control and mode pin monitoring. Signed-off-by:
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Geert Uytterhoeven authored
Add a device node for the RST module, which provides a.o. reset control and mode pin monitoring. Signed-off-by:
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Geert Uytterhoeven authored
Add a device node for the RST module, which provides a.o. reset control and mode pin monitoring. Signed-off-by: -
Geert Uytterhoeven authored
Add a device node for the RST module, which provides a.o. reset control and mode pin monitoring. Signed-off-by:
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Geert Uytterhoeven authored
Add a device node for the RST module, which provides a.o. reset control and mode pin monitoring. Signed-off-by:
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Geert Uytterhoeven authored
Add a device node for the RESET/WDT module, which provides a.o. reset control, mode pin monitoring, and watchdog control. Signed-off-by:
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Geert Uytterhoeven authored
Add a device node for the RESET/WDT module, which provides a.o. reset control, mode pin monitoring, and watchdog control. Signed-off-by:
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Geert Uytterhoeven authored
Add a driver for the Renesas R-Car Gen1 RESET/WDT and R-Car Gen2/Gen3 and RZ/G RST module. For now this driver just provides an API to obtain the state of the mode pins, as latched at reset time. As this is typically called from the probe function of a clock driver, which can run much earlier than any initcall, calling rcar_rst_read_mode_pins() just forces an early initialization of the driver. Despite the current simple and almost identical handling for all supported SoCs, the driver matches against SoC-specific compatible values, as the features provided by the hardware module differ a lot across the various SoC families and members. Signed-off-by:
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Geert Uytterhoeven authored
Add DT bindings for the Renesas R-Car Reset Controller (R-Car Gen1 RESET/WDT and R-Car Gen2/Gen3 and RZ/G RST). As the features provided by the hardware module differ a lot across the various SoC families and members, only SoC-specific compatible values are defined. For now we use the RST only for providing access to the state of the mode pins, which is needed by the clock driver. Signed-off-by:
Magnus Damm <damm+renesas@opensource.se> Acked-by:
Philipp Zabel <p.zabel@pengutronix.de> Acked-by:
Rob Herring <robh@kernel.org>
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Laurent Pinchart authored
Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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Laurent Pinchart authored
Signed-off-by:
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Laurent Pinchart authored
Signed-off-by:
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Geert Uytterhoeven authored
Signed-off-by: -
Ramesh Shanmugasundaram authored
This patch adds DRIF module clocks for r8a7796 SoC. Signed-off-by:
Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Acked-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
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- 17 Oct, 2016 5 commits
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Geert Uytterhoeven authored
The intention was to enable the checks if debugging is enabled, not disabled. Fixes: f793d1e5 ("clk: shmobile: Add new CPG/MSSR driver core") Signed-off-by:
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Geert Uytterhoeven authored
The R-Car Gen3 CPG/MSSR driver uses a mix of clk_readl()/clk_writel() and readl()/writel() to access the clock registers. Settle on the generic readl()/writel(). Signed-off-by:
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Geert Uytterhoeven authored
The Renesas CPG/MSSR driver core uses a mix of clk_readl()/clk_writel() and readl()/writel() to access the clock registers. Settle on the generic readl()/writel(). Signed-off-by:
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Ulrich Hecht authored
Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by:
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Ulrich Hecht authored
Signed-off-by:
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