- 15 Jul, 2016 7 commits
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Huang Rui authored
Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Huang Rui authored
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Huang Rui authored
The ucode_start_address would be used on powerplay of iceland. Signed-off-by:
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Huang Rui authored
SDMA firmware will be loaded by SMU manager if powerplay is enabled. So it needn't load at SDMA. Signed-off-by:
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Huang Rui authored
Rename smumgr.h to smum.h, because smum.h is to align with the dpm of other chips and we will use "iceland_smumgr" at powerplay in following patches. Signed-off-by:
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Alex Deucher authored
Still some stability issues under certain workloads. Reviewed-by:
Tom St Denis <tom.stdenis@amd.com> Signed-off-by:
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Matthias Beyer authored
Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
Matthias Beyer <mail@beyermatthias.de> Signed-off-by:
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- 14 Jul, 2016 12 commits
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Christian König authored
This is a minor interface change, but clearly won't break anything. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Christian König authored
Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Christian König authored
A little fallout from "drm/amdgpu: sanitize fence numbers", we sometimes need to signal all fences in the ring. Signed-off-by:
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Christian König authored
Otherwise we can run into the following situation: 1. Process A grabs ID 1 for ring 0. 2. Process B grabs ID 1 for ring 0. 3. Process A grabs ID 1 for ring 1. 4. Process A tries to reuse ID1 for ring 0 but things he doesn't need to flush. v2: check the context of the flush fence instead of messing with the owner field. Signed-off-by:
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Alex Deucher authored
Same interface as other UNIPHY blocks Signed-off-by: -
Alex Deucher authored
Same interface as other UNIPHY blocks Signed-off-by: -
Christian König authored
We already waited for the fence, so waiting for the registers is completely pointless and just copy & pasted from the ring test. Signed-off-by:
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Christian König authored
Reference should be taken when we make the assignment, not anywhere else. Signed-off-by:
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Christian König authored
Cleanup 80 chars limit. Signed-off-by:
Alexandre Demers <alexandre.f.demers@gmail.com> Signed-off-by:
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Christian König authored
We always used updated firmware for amdgpu, so this actually should work fine. Signed-off-by:
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Christian König authored
Fix 80 chars issues and remove some dead code as well. Signed-off-by:
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Christian König authored
Looks like the VCE block sometimes still sends nonsense fence numbers on startup. Signed-off-by:
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- 08 Jul, 2016 1 commit
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Alex Deucher authored
Atom tables are in LE format. Signed-off-by:
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- 07 Jul, 2016 20 commits
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Rex Zhu authored
if atomctrl_get_voltage_evv_on_sclk_ai returns non zero (fail) in the expansion of the PP_ASSERT_WITH_CODE macro the continue will actually do nothing, So invalid voltage will be added to ppbable. Signed-off-by:
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Rex Zhu authored
Create a GC_CAC_IND_INDEX/DATA pair of funcitons to program all the CAC registers Signed-off-by:
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Rex Zhu authored
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Rex Zhu authored
v1: delete some comflict definitions between polaris and fiji. Signed-off-by:
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Ken Wang authored
those register mask definitions are different in polaris compare to former gfx 8 gpus, so remove them from misusing. Signed-off-by:
Ken Wang <Qingqing.Wang@amd.com> Reviewed-by:
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Rex Zhu authored
SMC requires master switch bit to be set. Signed-off-by:
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Rex Zhu authored
the num of shade engine was needed to measure the activity of the graphics core and to enable di/dt feature. Signed-off-by:
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Alex Deucher authored
Not used anymore. Reviewed-by:
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Tom St Denis authored
s/AMD_FAMILY_/AMDGPU_FAMILY_/ Signed-off-by:
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Chunming Zhou authored
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Chunming Zhou authored
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Chunming Zhou authored
V3: directly use pd_addr. Signed-off-by:
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Chunming Zhou authored
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Chunming Zhou authored
which avoids job->vm_pd_addr be changed. V2: pass job structure to amdgpu_vm_grab_id and amdgpu_vm_flush directly. Signed-off-by:
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Chunming Zhou authored
Which is to recover hw jobs when gpu reset. Signed-off-by:
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Chunming Zhou authored
After all hw jobs are reset, hw fence is meaningless, so force_completion Cc: William Lewis <minutemaidpark@hotmail.com> Signed-off-by:
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Chunming Zhou authored
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Chunming Zhou authored
amd_sched_hw_job_reset will remove callback from hw fence. Signed-off-by:
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Chunming Zhou authored
Parent of sched fence is hw fence which is to signal sched fence. Signed-off-by:
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Chunming Zhou authored
Previous vm fault is since page talbe losts connection with vmid after gpu reset. Now the issue is fixed by recovery. No need more. If we want to save vram for some EDC card, we will need to consider a complete solution. Signed-off-by:
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