- 01 Apr, 2020 40 commits
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Alex Sierra authored
call psp to program ih cntl in SR-IOV if supported on Navi and Arcturus. Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Sierra authored
Support added into IH to enable ring1 and ring2 for navi10_ih. Signed-off-by:
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Alex Sierra authored
[Why] nbio v7.4 size of ih doorbell range is 64 bit. This requires 2 DWords per register. [How] Change ih doorbell size from 2 to 4. This means two Dwords per ring. Current configuration uses two ih rings. Signed-off-by:
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Alex Sierra authored
[Why] Previously these registers were set to 0. This was causing an infinite retry on the UTCL1 RB, preventing higher priority RB such as paging RB. [How] Set to one the SDMAx_UTLC1_TIMEOUT registers for all SDMAs on Vega10, Vega12, Vega20 and Arcturus. Signed-off-by:
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Evan Quan authored
Backtrace on gpu recover test on Navi10. [ 1324.516681] RIP: 0010:amdgpu_ras_set_error_query_ready+0x15/0x20 [amdgpu] [ 1324.523778] Code: 4c 89 f7 e8 cd a2 a0 d8 e9 99 fe ff ff 45 31 ff e9 91 fe ff ff 0f 1f 44 00 00 55 48 85 ff 48 89 e5 74 0e 48 8b 87 d8 2b 01 00 <40> 88 b0 38 01 00 00 5d c3 66 90 0f 1f 44 00 00 55 31 c0 48 85 ff [ 1324.543452] RSP: 0018:ffffaa1040e4bd28 EFLAGS: 00010286 [ 1324.549025] RAX: 0000000000000000 RBX: ffff911198b20000 RCX: 0000000000000000 [ 1324.556217] RDX: 00000000000c0a01 RSI: 0000000000000000 RDI: ffff911198b20000 [ 1324.563514] RBP: ffffaa1040e4bd28 R08: 0000000000001000 R09: ffff91119d0028c0 [ 1324.570804] R10: ffffffff9a606b40 R11: 0000000000000000 R12: 0000000000000000 [ 1324.578413] R13: ffffaa1040e4bd70 R14: ffff911198b20000 R15: 0000000000000000 [ 1324.586464] FS: 00007f4441cbf540(0000) GS:ffff91119ed80000(0000) knlGS:0000000000000000 [ 1324.595434] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 1324.601345] CR2: 0000000000000138 CR3: 00000003fcdf8004 CR4: 00000000003606e0 [ 1324.608694] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 1324.616303] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 1324.623678] Call Trace: [ 1324.626270] amdgpu_device_gpu_recover+0x6e7/0xc50 [amdgpu] [ 1324.632018] ? seq_printf+0x4e/0x70 [ 1324.636652] amdgpu_debugfs_gpu_recover+0x50/0x80 [amdgpu] [ 1324.643371] seq_read+0xda/0x420 [ 1324.647601] full_proxy_read+0x5c/0x90 [ 1324.652426] __vfs_read+0x1b/0x40 [ 1324.656734] vfs_read+0x8e/0x130 [ 1324.660981] ksys_read+0xa7/0xe0 [ 1324.665201] __x64_sys_read+0x1a/0x20 [ 1324.669907] do_syscall_64+0x57/0x1c0 [ 1324.674517] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 1324.680654] RIP: 0033:0x7f44417cf081 Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
John Clements <John.Clements@amd.com> Signed-off-by:
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Tom St Denis authored
Clean up the smu10, smu12, and gfx9 drivers to use headers for registers instead of hardcoding in the C source files. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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xinhui pan authored
We have three ib pools, they are normal, VM, direct pools. Any jobs which schedule IBs without dependence on gpu scheduler should use DIRECT pool. Any jobs schedule direct VM update IBs should use VM pool. Any other jobs use NORMAL pool. v2: squash in coding style fix Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Wyatt Wood authored
[Why] Can't call dmub_abm_enable_fractional_pwm from dmub_abm_create as dmub_srv is still null at this init stage, and therefore can't call to fw. [How] Move call to dmub_abm_init_backlight. This should be the first call from the driver for ABM. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Wyatt Wood authored
[Why] Moving ABM from DMCU to DMCUB. [How] Add ABM driver files and implementation. Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Jiawei authored
extend compute lockup timeout to 60000 for SR-IOV. Reviewed-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
Jiawei <Jiawei.Gu@amd.com> Signed-off-by:
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Emily Deng authored
As no need to support vcn decode feature, so disable the ring for SR-IOV. Signed-off-by:
Monk Liu <monk.liu@amd.com> Signed-off-by:
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Monk Liu authored
if host support new handshake we only need to enter fullaccess_mode in ip_init() part, otherwise we need to do it before reading vbios (becuase host prepares vbios for VF only after received REQ_GPU_INIT event under legacy handshake) Signed-off-by:
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Monk Liu authored
what: 1)move timtout setting before ip_early_init to reduce exclusive mode cost for SRIOV 2)move ip_discovery_init() to inside of amdgpu_discovery_reg_base_init() it is a prepare for the later upcoming patches. why: in later upcoming patches we would use a new mailbox event -- "req_gpu_init_data", which is a callback hooked in adev->virt.ops and this callback send a new event "REQ_GPU_INIT_DAT" to host to notify host to do some preparation like "IP discovery/vbios on the VF FB" and this callback must be: A) invoked after set_ip_block() because virt.ops is configured during set_ip_block() B) invoked before ip_discovery_init() becausen ip_discovery_init() need host side prepares everything in VF FB first. current place of ip_discovery_init() is before we can invoke callback of adev->virt.ops, thus we must move ip_discovery_init() to a place after the adev->virt.ops all settle done, and the perfect place is in amdgpu_discovery_reg_base_init() Signed-off-by:
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Monk Liu authored
by this new handshake host side can prepare vbios/ip-discovery and pf&vf exchange data upon recieving this request without stopping world switch. this way the world switch is less impacted by VF's exclusive mode request Signed-off-by:
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Monk Liu authored
what: with the new "req_init_data" handshake we need to use mailbox before do IP discovery, so in mxgpu_nv.c file the original SOC15_REG method won'twork because that depends on IP discovery complete first. how: so the solution is to always use static MMIO offset for NV+ mailbox registers. HW team confirm us all MAILBOX registers will be at the same offset for all ASICs, no IP discovery needed for those registers Signed-off-by:
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Monk Liu authored
1) modify xgpu_nv_send_access_requests to support new idh request 2) introduce new function: req_gpu_init_data() which is used to notify host to prepare vbios/ip-discovery/pfvf exchange Signed-off-by:
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Monk Liu authored
new idh_request and ihd_event to prepare for the new handshake protocol implementation later Signed-off-by:
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Monk Liu authored
1) drop the headers from AI in mxgpu_nv.c, should refer to mxgpu_nv.h 2) the IDH_EVENT_MAX is not used and not aligned with host side so drop it 3) the IDH_TEXT_MESSAG was provided in host but not defined in guest Signed-off-by:
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Tom St Denis authored
The PWR block was merged into the SMUIO block by revision 12 so we add that to the smuio_12_0_0 headers. (v2): Drop nonsensical smuio_10_0_0 header Signed-off-by:
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Tom St Denis authored
The register is part of the PWR block not the GC block. Move to its own header. Signed-off-by:
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Tom St Denis authored
This register is needed by umr. Signed-off-by:
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Chen Zhou authored
The conversion to bool is not needed, remove it. Signed-off-by:
Chen Zhou <chenzhou10@huawei.com> Signed-off-by:
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Masahiro Yamada authored
This beautifies the build log. [Before] HOSTCC drivers/gpu/drm/radeon/mkregtable MKREGTABLE drivers/gpu/drm/radeon/r100_reg_safe.h MKREGTABLE drivers/gpu/drm/radeon/rn50_reg_safe.h CC [M] drivers/gpu/drm/radeon/r100.o MKREGTABLE drivers/gpu/drm/radeon/r300_reg_safe.h CC [M] drivers/gpu/drm/radeon/r300.o [After] HOSTCC drivers/gpu/drm/radeon/mkregtable MKREG drivers/gpu/drm/radeon/r100_reg_safe.h MKREG drivers/gpu/drm/radeon/rn50_reg_safe.h CC [M] drivers/gpu/drm/radeon/r100.o MKREG drivers/gpu/drm/radeon/r300_reg_safe.h CC [M] drivers/gpu/drm/radeon/r300.o Signed-off-by:
Masahiro Yamada <masahiroy@kernel.org> Signed-off-by:
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Masahiro Yamada authored
This Makefile repeats similar build rules. Use a pattern rule. Signed-off-by:
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Masahiro Yamada authored
if_changed must have FORCE as a prerequisite, and the targets must be added to 'targets'. Signed-off-by:
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Masahiro Yamada authored
A header include path without $(srctree)/ is suspicious because it does not work with O= builds. You can build drivers/gpu/drm/radeon/ without this include path. Signed-off-by:
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Emily Deng authored
As the VCN firmware will not use vf vmr now. And new psp policy won't support set tmr now. For driver compatible issue, ignore the not support error. Signed-off-by:
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Emily Deng authored
Add 4k resolution for virtual connector. Signed-off-by:
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Emily Deng authored
The crtc num is determined by virtual_display parameter. Signed-off-by:
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John Clements authored
added flag to ras context to indicate if ras query functionality is ready Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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John Clements authored
added mechanism to clear xgmi ras status inbetween error queries Reviewed-by:
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Monk Liu authored
we need to move virt detection much earlier because: 1) HW team confirms us that RCC_IOV_FUNC_IDENTIFIER will always be at DE5 (dw) mmio offset from vega10, this way there is no need to implement detect_hw_virt() routine in each nbio/chip file. for VI SRIOV chip (tonga & fiji), the BIF_IOV_FUNC_IDENTIFIER is at 0x1503 2) we need to acknowledged we are SRIOV VF before we do IP discovery because the IP discovery content will be updated by host everytime after it recieved a new coming "REQ_GPU_INIT_DATA" request from guest (there will be patches for this new handshake soon). Signed-off-by:
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Monk Liu authored
Signed-off-by:
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Monk Liu authored
those two headers are not needed for ip discovery Signed-off-by:
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Kent Russell authored
Ensure that when we memcpy, we don't end up copying more data than the struct supports. For now, this is 16 characters for product number and serial number, and 32 chars for product name Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
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Kent Russell authored
Reporting the fw_version just returns 0, the actual version is kept as ta_*_ucode_version. This is the same as the feature reported in the amdgpu_firmware_info debugfs file. Signed-off-by:
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John Clements authored
added asic support checking function to be filled in by supported asic types Reviewed-by:
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Tom St Denis authored
The registers are needed for umr and not in the headers. I left them in the gfx_v9_0.c since it includes 9.0 and 9.4 headers and including 9.1 headers would result in a lot of duplicate registers clashing. Signed-off-by:
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Kent Russell authored
Add the amdgpu.rst tie-ins for the unique_id documentation Signed-off-by:
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