- 24 Nov, 2020 5 commits
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Fabio Estevam authored
Since 5.10-rc1 i.MX is a devicetree-only platform, so simplify the code by removing the unused non-DT support. Signed-off-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20201124143405.2764-1-festevam@gmail.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Vinod Koul authored
This controller provides DMAengine capabilities for a variety of peripheral buses such as I2C, UART, and SPI. By using GPI dmaengine driver, bus drivers can use a standardize interface that is protocol independent to transfer data between memory and peripheral. Link: https://lore.kernel.org/r/20201109085450.24843-4-vkoul@kernel.orgSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Vinod Koul authored
Some complex dmaengine controllers have capability to program the peripheral device, so pass on the peripheral configuration as part of dma_slave_config Link: https://lore.kernel.org/r/20201109085450.24843-3-vkoul@kernel.orgSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Vinod Koul authored
Add devicetree binding documentation for GPI DMA controller implemented on Qualcomm SoCs Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201109085450.24843-2-vkoul@kernel.orgSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Jonathan McDowell authored
Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA controller found in the MSM8x60 and IPQ/APQ8064 platforms. The ADM supports both memory to memory transactions and memory to/from peripheral device transactions. The controller also provides flow control capabilities for transactions to/from peripheral devices. The initial release of this driver supports slave transfers to/from peripherals and also incorporates CRCI (client rate control interface) flow control. The hardware only supports a 32 bit physical address, so specifying !PHYS_ADDR_T_64BIT gives maximum COMPILE_TEST coverage without having to spend effort on kludging things in the code that will never actually be needed on real hardware. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Thomas Pedersen <twp@codeaurora.org> Signed-off-by: Jonathan McDowell <noodles@earth.li> Link: https://lore.kernel.org/r/20201114140233.GM32650@earth.liSigned-off-by: Vinod Koul <vkoul@kernel.org>
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- 18 Nov, 2020 5 commits
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Fabio Estevam authored
Since 5.10-rc1 i.MX is a devicetree-only platform and the existing .id_table support in this driver was only useful for old non-devicetree platforms. Signed-off-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20201116202403.29749-1-festevam@gmail.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Yangtao Li authored
The dma of a100 is similar to h6, with some minor changes to support greater addressing capabilities. Add support for it. Signed-off-by: Yangtao Li <frank@allwinnertech.com> Link: https://lore.kernel.org/r/719852c6a9a597bd2e82d01a268ca02b9dee826c.1604988979.git.frank@allwinnertech.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Yangtao Li authored
Add a binding for A100's dma controller. Signed-off-by: Yangtao Li <frank@allwinnertech.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/f15a18e9b8868e8853db1b5a3d1e411b0ac1c63a.1604988979.git.frank@allwinnertech.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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周琰杰 (Zhou Yanjie) authored
Add the dmaengine bindings for the X2000 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201107122016.89859-3-zhouyanjie@wanyeetech.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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周琰杰 (Zhou Yanjie) authored
Add the dmaengine bindings for the JZ4775 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201107122016.89859-2-zhouyanjie@wanyeetech.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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- 09 Nov, 2020 15 commits
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Barry Song authored
Running in hardIRQ, disabling IRQ is redundant since hardIRQ has disabled IRQ. This patch removes the irqsave and irqstore to save some instruction cycles. Signed-off-by: Barry Song <song.bao.hua@hisilicon.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Cc: Daniel Mack <daniel@zonque.org> Cc: Haojian Zhuang <haojian.zhuang@gmail.com> Link: https://lore.kernel.org/r/20201027215252.25820-11-song.bao.hua@hisilicon.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Barry Song authored
Running in hardIRQ, disabling IRQ is redundant since hardIRQ has disabled IRQ. This patch removes the irqsave and irqstore to save some instruction cycles. Signed-off-by: Barry Song <song.bao.hua@hisilicon.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20201027215252.25820-10-song.bao.hua@hisilicon.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Barry Song authored
Running in hardIRQ, disabling IRQ is redundant since hardIRQ has disabled IRQ. This patch removes the irqsave and irqstore to save some instruction cycles. Signed-off-by: Barry Song <song.bao.hua@hisilicon.com> Link: https://lore.kernel.org/r/20201027215252.25820-9-song.bao.hua@hisilicon.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Barry Song authored
Running in hardIRQ, disabling IRQ is redundant since hardIRQ has disabled IRQ. This patch removes the irqsave and irqstore to save some instruction cycles. Signed-off-by: Barry Song <song.bao.hua@hisilicon.com> Acked-by: Zhou Wang <wangzhou1@hisilicon.com> Link: https://lore.kernel.org/r/20201027215252.25820-8-song.bao.hua@hisilicon.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Barry Song authored
Running in hardIRQ, disabling IRQ is redundant since hardIRQ has disabled IRQ. This patch removes the irqsave and irqstore to save some instruction cycles. Signed-off-by: Barry Song <song.bao.hua@hisilicon.com> Link: https://lore.kernel.org/r/20201027215252.25820-7-song.bao.hua@hisilicon.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Barry Song authored
Running in hardIRQ, disabling IRQ is redundant since hardIRQ has disabled IRQ. This patch removes the irqsave and irqstore to save some instruction cycles. Signed-off-by: Barry Song <song.bao.hua@hisilicon.com> Link: https://lore.kernel.org/r/20201027215252.25820-6-song.bao.hua@hisilicon.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Barry Song authored
Running in hardIRQ, disabling IRQ is redundant since hardIRQ has disabled IRQ. This patch removes the irqsave and irqstore to save some instruction cycles. Signed-off-by: Barry Song <song.bao.hua@hisilicon.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Cc: Laxman Dewangan <ldewangan@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Link: https://lore.kernel.org/r/20201027215252.25820-5-song.bao.hua@hisilicon.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Barry Song authored
Running in hardIRQ, disabling IRQ is redundant since hardIRQ has disabled IRQ. This patch removes the irqsave and irqstore to save some instruction cycles. Signed-off-by: Barry Song <song.bao.hua@hisilicon.com> Cc: Green Wan <green.wan@sifive.com> Link: https://lore.kernel.org/r/20201027215252.25820-4-song.bao.hua@hisilicon.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Barry Song authored
Running in hardIRQ, disabling IRQ is redundant since hardIRQ has disabled IRQ. This patch removes the irqsave and irqstore to save some instruction cycles. Signed-off-by: Barry Song <song.bao.hua@hisilicon.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lore.kernel.org/r/20201027215252.25820-3-song.bao.hua@hisilicon.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Barry Song authored
Running in hardIRQ, disabling IRQ is redundant since hardIRQ has disabled IRQ. This patch removes the irqsave and irqstore to save some instruction cycles. Signed-off-by: Barry Song <song.bao.hua@hisilicon.com> Link: https://lore.kernel.org/r/20201027215252.25820-2-song.bao.hua@hisilicon.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Grygorii Strashko authored
The NAVSS UDMA will stuck if target IP module is disabled by PM while PSI-L threads are paired UDMA<->IP and no further transfers is possible. This could be the case for IPs J721E Main CPSW (cpsw9g). Hence, to avoid such situation do PSI-L threads pairing only when UDMA channel is going to be enabled as at this time DMA consumer module expected to be active already. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lore.kernel.org/r/20201030203000.4281-1-grygorii.strashko@ti.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Andy Shevchenko authored
ifdeffery is prone to errors and makes code harder to read. Switch to use __maybe_unused instead of ifdeffery. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20201104103131.89907-1-andriy.shevchenko@linux.intel.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Andy Shevchenko authored
When consumer requests channel power on the DMA controller device and otherwise on the freeing channel resources. Note, in some cases consumer acquires channel at the ->probe() stage and releases it at the ->remove() stage. It will mean that DMA controller device will be powered during all this time if there is no assist from hardware to idle it. The above mentioned cases should be investigated separately and individually. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Link: https://lore.kernel.org/r/20201103183938.64752-1-andriy.shevchenko@linux.intel.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Dave Jiang authored
Convert table offset multiplier magic number to a define. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/160407311690.839435.6941865731867828234.stgit@djiang5-desk3.ch.intel.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Dave Jiang authored
Create helper macros to make group offset calculation more readable. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/160407294683.839093.10740868559754142070.stgit@djiang5-desk3.ch.intel.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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- 30 Oct, 2020 12 commits
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Dave Jiang authored
Add the sysfs attribute bits in ABI/stable for shared wq support. Signed-off-by: Jing Lin <jing.lin@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Link: https://lore.kernel.org/r/160382008649.3911367.10851752182908509837.stgit@djiang5-desk3.ch.intel.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Dave Jiang authored
Add code to "complete" a descriptor when the descriptor or its completion address hit a fault error when SVA mode is being used. This error can be triggered due to bad programming by the user. A lock is introduced in order to protect the descriptor completion lists since the fault handler will run from the system work queue after being scheduled in the interrupt handler. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Link: https://lore.kernel.org/r/160382008092.3911367.12766483427643278985.stgit@djiang5-desk3.ch.intel.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Dave Jiang authored
Add shared workqueue support that includes the support of Shared Virtual memory (SVM) or in similar terms On Demand Paging (ODP). The shared workqueue uses the enqcmds command in kernel and will respond with retry if the workqueue is full. Shared workqueue only works when there is PASID support from the IOMMU. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Link: https://lore.kernel.org/r/160382007499.3911367.26043087963708134.stgit@djiang5-desk3.ch.intel.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Krzysztof Kozlowski authored
The xor_hw_desc local variable is assigned but never read: drivers/dma/ppc4xx/adma.c: In function ‘ppc440spe_desc_set_src_mult’: drivers/dma/ppc4xx/adma.c:562:17: warning: variable ‘xor_hw_desc’ set but not used [-Wunused-but-set-variable] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201019155756.21445-2-krzk@kernel.orgSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Krzysztof Kozlowski authored
The ppc440spe_adma_chan_list file-scope variable is not used outside of the unit so it can be made static. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201019155756.21445-1-krzk@kernel.orgSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Eugen Hristev authored
The sama7g5 version of the XDMAC supports priority configuration and outstanding capabilities. Add defines for the specific registers for this configuration, together with recommended settings. However the settings are very different if the XDMAC is a mem2mem or a per2mem controller. Thus, we need to differentiate according to device tree property. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Link: https://lore.kernel.org/r/20201016093918.290137-1-eugen.hristev@microchip.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Eugen Hristev authored
SAMA7G5 SoC uses a slightly different variant of the AT_XDMAC. Added support by a new compatible and a layout struct that copes to the specific version considering the compatible string. Only the differences in register map are present in the layout struct. I reworked the register access for this part that has the differences. Also the Source/Destination Interface bits are no longer valid for this variant of the XDMAC. Thus, the layout also has a bool for specifying whether these bits are required or not. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Link: https://lore.kernel.org/r/20201016093850.290053-1-eugen.hristev@microchip.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Eugen Hristev authored
The PERID in the CC register for mem2mem operations must match an unused PERID. The PERID field is 7 bits, but the selected value is 0x3f. On later products we can have more reserved PERIDs for actual peripherals, thus this needs to be increased to maximum size. Changing the value to 0x7f, which is the maximum for 7 bits field. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20201016093725.289880-1-eugen.hristev@microchip.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Eugen Hristev authored
Add compatible to sama7g5 SoC. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201016081754.288488-1-eugen.hristev@microchip.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Surendran K authored
_setup_req(..) never returns negative value. Hence the condition ret < 0 is never met Signed-off-by: Surendran K <surendran.k@samsung.com> Link: https://lore.kernel.org/r/20201016103347.63084-1-surendran.k@samsung.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Gustavo A. R. Silva authored
Make use of the new struct_size() helper instead of the offsetof() idiom. Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Link: https://lore.kernel.org/r/20201008141828.GA20325@embeddedorSigned-off-by: Vinod Koul <vkoul@kernel.org>
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Dave Jiang authored
DSA spec v1.1 [1] updated to include a stride size register for WQ configuration that will specify how much space is reserved for the WQ configuration register set. This change is expected to be in the final gen1 DSA hardware. Fix the driver to use WQCFG_OFFSET() for all WQ offset calculation and fixup WQCFG_OFFSET() to use the new calculated wq size. [1]: https://software.intel.com/content/www/us/en/develop/download/intel-data-streaming-accelerator-preliminary-architecture-specification.html Fixes: bfe1d560 ("dmaengine: idxd: Init and probe for Intel data accelerators") Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/160383444959.48058.14249265538404901781.stgit@djiang5-desk3.ch.intel.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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- 25 Oct, 2020 3 commits
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Linus Torvalds authored
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Joe Perches authored
Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Conversion done using the script at: https://lore.kernel.org/lkml/75393e5ddc272dc7403de74d645e6c6e0f4e70eb.camel@perches.com/2-convert_section.plSigned-off-by: Joe Perches <joe@perches.com> Reviewed-by: Nick Desaulniers <ndesaulniers@gooogle.com> Reviewed-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Rasmus Villemoes authored
tid_addr is not a "pointer to (pointer to int in userspace)"; it is in fact a "pointer to (pointer to int in userspace) in userspace". So sparse rightfully complains about passing a kernel pointer to put_user(). Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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