- 15 Aug, 2019 22 commits
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David Galiffi authored
[WHY] We require a method to perform synchronous link training. [HOW] Sync LT is broken into 3 basic steps. "Begin" starts the state machine, and resets "preferred" link settings. "Attempt" will attempt to train the link with a given set of training parameters. "End" stops the state machine, and will optionally disable the link phy. Between "Begin" and "End" DPCD:600h must not be set to "2" (D3:Powered Down). Between "Begin" and "End", there may be multiple "Attempts" with different training parameters. Signed-off-by:
David Galiffi <david.galiffi@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Julian Parkin authored
Add DCN20 common register list that contains registers shared between DCN20 generations. Signed-off-by:
Julian Parkin <julian.parkin@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Vitaly Prosyak authored
[Why & How] Support degamma ROM and RAM based on hardware capabilities. Some refactoring into color module Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
Gary Kattan <Gary.Kattan@amd.com> Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
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Bayan Zabihiyan authored
[Why] The math on deciding on how many "frames to insert" sometimes sent us over the max refresh rate. Also integer overflow can occur if we have high refresh rates. [How] Instead of clipping the frame duration such that it doesn’t go below the min, just remove a frame from the number of frames to insert. + Use unsigned long long for intermediate calculations to prevent integer overflow. Signed-off-by:
Bayan Zabihiyan <bayan.zabihiyan@amd.com> Reviewed-by:
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Anthony Koo authored
[Why] When endpoint is at the boundary of a region, such as at 2^0=1 we find that the last segment has a sharp slope and some points are clipped at the top. [How] If end point is 1, which is exactly at the 2^0 region boundary, we need to program an additional region beyond this point. Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
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Wenjing Liu authored
[why] hdmi data scramble and tmds rate is not reset during pipe reset. [how] reset hdmi tmds rate and data scramble on pipe reset Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Wenjing Liu authored
[why] drr is still enabled after driver is unloaded causing black screen [how] disable drr during pipe reset. Signed-off-by:
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Yongqiang Sun authored
Add to clk_mgr_internal struct, for future use. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Yongqiang Sun authored
For use by future ASICs Signed-off-by:
Sung Lee <sung.lee@amd.com> Signed-off-by:
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Christian König authored
The spsc_queue_peek function is accessing queue->head which belongs to the consumer thread and shouldn't be accessed by the producer This is fixing a rare race condition when destroying entities. Signed-off-by:
Christian König <christian.koenig@amd.com> Acked-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Monk.liu@amd.com Signed-off-by:
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Stephen Rothwell authored
Fixes: 6a7a0bdb ("drm/amdgpu: add psp_v12_0 for renoir (v2)") Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
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Colin Ian King authored
There is a spelling mistake in a pr_err error message. Fix it. Also add a space after a comma to clean up a checkpatch warning. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Tao Zhou authored
get mmhub ea ras error count by accessing EDC_CNT register Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Kevin Wang authored
simplify driver code. Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
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Kevin Wang authored
fix typo error: change function name from "amdgput_ctx_total_num_entities" to "amdgpu_ctx_total_num_entities". Signed-off-by:
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Kevin Wang authored
the direct send message to smc to set hard clokc will failed when smc clock dpm feature is disabled. so use function of smu_set_hard_freq_range to replace it. the function will check feature enablement. eg: when uclk (mclk) dpm feature is disabled on navi10 [ 300.675901] amdgpu: [powerplay] failed send message: SetHardMinByFreq(28) param: 0x00020064 response 0xfffffffb Signed-off-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Chengming Gui authored
add arcturus_is_dpm_running function Signed-off-by:
Chengming Gui <Jack.Gui@amd.com> Reviewed-by:
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Chengming Gui authored
remove redundancy debug log about smu unsupported features Signed-off-by:
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Christoph Hellwig authored
Use dma_set_mask_and_coherent to set both masks in one go, and remove the no longer required fallback, as the kernel now always accepts larger than required DMA masks. Fail the driver probe if we can't set the DMA mask, as that means the system can only support a larger mask. Reviewed-by:
Christoph Hellwig <hch@lst.de> Signed-off-by:
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Christoph Hellwig authored
Use dma_set_mask_and_coherent to set both masks in one go, and remove the no longer required fallback, as the kernel now always accepts larger than required DMA masks. Fail the driver probe if we can't set the DMA mask, as that means the system can only support a larger mask. Reviewed-by:
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Christoph Hellwig authored
amdgpu uses a need_dma32 flag to indicate to the drm core that some allocations need to be done using GFP_DMA32, but it only checks the device addressing capabilities to make that decision. Unfortunately PCIe root ports that have limited addressing exist as well. Use the dma_addressing_limited instead to also take those into account. Reviewed-by:
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Christoph Hellwig authored
radeon uses a need_dma32 flag to indicate to the drm core that some allocations need to be done using GFP_DMA32, but it only checks the device addressing capabilities to make that decision. Unfortunately PCIe root ports that have limited addressing exist as well. Use the dma_addressing_limited instead to also take those into account. Reviewed-by:
Atish Patra <Atish.Patra@wdc.com> Signed-off-by:
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- 12 Aug, 2019 18 commits
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Alex Deucher authored
The current code won't likely work on production hw when it ships so leave it as experimental until it's ready. Acked-by:
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Huang Rui authored
Renoir need not load mec2 jump table with psp. Acked-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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Huang Rui authored
PSP has issue for renoir, that will cause VCN fw failed to be loaded. So use direct loading for the moment till the issue is addressed. Acked-by:
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Aaron Liu authored
By default, set amdgpu ucode type to AMDGPU_FW_LOAD_PSP. Acked-by:
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Aaron Liu authored
enable gfx_v9_0_init_lbpw for renoir Acked-by:
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Aaron Liu authored
enable gfx power gating for renoir Acked-by:
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Aaron Liu authored
enable gfx&common clock gating for renoir Acked-by:
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Leo Liu authored
Thus enable VCN2.0 for Renoir Acked-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Leo Liu authored
Add VCN range aperture to NBIO 7.0 v2: rebase (Alex) Acked-by:
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Leo Liu authored
By adding new Renoir VCN firmware Acked-by:
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Huang Rui authored
This patch adds sdma golden settings for renoir asic. Acked-by:
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Huang Rui authored
This patch adds gfx golden settings for renoir real asic. v2: update settings (Alex) Acked-by:
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Aaron Liu authored
1. Add psp ip block 2. Use direct loading type by default and it can also config psp loading type. 3. Bypass sos fw loading and xgmi&ras interface v2: drop TA loading Acked-by:
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Aaron Liu authored
add gfx_v9_0_rlc_funcs for renoir Acked-by:
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Aaron Liu authored
add asic funcs for renoir, init soc15_asic_funcs Acked-by:
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Aaron Liu authored
Acked-by:
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Aaron Liu authored
In renoir's ih model, there's a change in mmIH_CHICKEN register, that limits IH to use physical address directly. Those chicken bits need to be programmed first. Acked-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
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Huang Rui authored
Add Renoir PCI id support. Acked-by:
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