- 03 Mar, 2016 14 commits
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Stephen Boyd authored
This flag is a no-op now. Remove usage of the flag. Reviewed-by:
Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
This flag is a no-op now. Remove usage of the flag. Acked-by:
Ulf Hansson <ulf.hansson@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Stephen Boyd authored
This flag is a no-op now. Remove usage of the flag. Acked-by:
Tero Kristo <t-kristo@ti.com> Signed-off-by:
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Stephen Boyd authored
This flag is a no-op now. Remove usage of the flag. Acked-by:
Rhyland Klein <rklein@nvidia.com> Acked-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
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Stephen Boyd authored
This flag is a no-op now. Remove usage of the flag. Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
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Stephen Boyd authored
This flag is a no-op now. Remove usage of the flag. Acked-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by:
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Stephen Boyd authored
This flag is a no-op now. Remove usage of the flag. Acked-by:
Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by:
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Stephen Boyd authored
This flag is a no-op now. Remove usage of the flag. Acked-by:
Joachim Eastwood <manabian@gmail.com> Signed-off-by:
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Stephen Boyd authored
This flag is a no-op now. Remove usage of the flag. Acked-by:
Shawn Guo <shawnguo@kernel.org> Signed-off-by:
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Stephen Boyd authored
This flag is a no-op now. Remove usage of the flag. Acked-by:
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Stephen Boyd authored
This flag is a no-op now. Remove usage of the flag. Acked-by:
James Liao <jamesjj.liao@mediatek.com> Signed-off-by:
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Stephen Boyd authored
This flag is a no-op now. Remove usage of the flag. Tested-by:
Leo Yan <leo.yan@linaro.org> Cc: Bintian Wang <bintian.wang@huawei.com> Cc: Zhangfei Gao <zhangfei.gao@linaro.org> Cc: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by:
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Stephen Boyd authored
This flag is a no-op now. Remove usage of the flag. Acked-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by:
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Stephen Boyd authored
This flag is a no-op now. Remove usage of the flag. Cc: Lee Jones <lee@kernel.org> Reviewed-by:
Eric Anholt <eric@anholt.net> Signed-off-by:
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- 02 Mar, 2016 7 commits
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Stephen Boyd authored
Merge tag 'imx-clk-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next Pull i.MX clk updates from Shawn Guo: The i.MX clock update for 4.6: - Add the clock driver support for the latest i.MX6 family SoCs addition - i.MX6QP. - Clean up the whitespace in i.MX6UL clock driver and add the missing KPP clock. - Correct pwm7 clock name in i.MX6UL clock driver. * tag 'imx-clk-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: clk: imx: add kpp clock for i.MX6UL clk: imx: whitespace cleanup; no functional change clk: imx: correct pwm7 clock name in driver for i.MX6UL clk: imx: Add clock support for imx6qp
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Stephen Boyd authored
Merge tag 'sunxi-clocks-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Pull Allwinner clk updates from Maxime Ripard: Allwinner clocks additions for 4.6 A bunch of things, mostly: - Finally switched everything over to OF_CLK_DECLARE, which should remove orphans clocks entirely - Reworked the clk-factors to be able to add new parameters - Improved the error reporting - A bunch of new clocks for new SoCs. * tag 'sunxi-clocks-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (25 commits) clk: sunxi: Add apb0 gates for H3 clk: sunxi: Improve divs_clk error handling and reporting clk: sunxi: improve divider_clk error handling and reporting clk: sunxi: improve mux_clk error handling and reporting clk: sunxi: Fix sun8i-a23-apb0-clk divider flags clk: sunxi: Remove clk_register_clkdev calls clk: sunxi: Remove old probe and protection code clk: sunxi: convert current clocks registration to CLK_OF_DECLARE clk: sunxi: Make clocks setup functions take const pointer clk: sunxi: Make clocks setup functions return their clock clk: sunxi: improve error reporting for the mux clock clk: sunxi: don't mark sun6i_ar100_data __initconst clk: sunxi: add bus gates for A83T clk: sunxi: Add apb0 gates for A83T clk: sunxi: rewrite sun8i-a23-mbus-clk using the simpler composite clk clk: sunxi: rewrite sun6i-ar100 using factors clk clk: sunxi: rewrite sun6i-a31-ahb1-clk using factors clk with custom recalc clk: sunxi: factors: Drop round_rate from clk ops clk: sunxi: factors: Support custom formulas clk: sunxi: factors: Consolidate get_factors parameters into a struct ...
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Stephen Boyd authored
The offset seems to have been copied from the sata clk. Fix it so that enabling the crypto engine source clk works. Tested-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Tested-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Fixes: 5f775498 ("clk: qcom: Fully support apq8064 global clock control") Signed-off-by:
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Michael Turquette authored
Conflicts: drivers/clk/Kconfig
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Stephen Boyd authored
drivers/clk/ti/clk-814x.c:34:12: warning: symbol 'dm814x_adpll_early_init' was not declared. Should it be static? drivers/clk/ti/clk-814x.c:58:12: warning: symbol 'dm814x_adpll_enable_init_clocks' was not declared. Should it be static? drivers/clk/ti/adpll.c:465 ti_adpll_recalc_rate() warn: should '__readw(d->regs + 20) << 18' be a 64 bit type? drivers/clk/ti/adpll.c:945 ti_adpll_probe() error: we previously assumed 'd->clocks' could be null (see line 921) The last one looks like a real bug because we don't return an error on allocation failure. Cc: Tero Kristo <t-kristo@ti.com> Tested-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
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Tony Lindgren authored
The arch independent drivers can be build testeed with COMPILE_TEST. Let's allow that for drivers/clk/ti. Signed-off-by:
Michael Turquette <mturquette@baylibre.com>
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Tony Lindgren authored
On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The ADPLLs have several dividers and muxes controlled by a shared control register for each PLL. Note that for the clocks to work as device drivers for booting on dm814x, this patch depends on "ARM: OMAP2+: Change core_initcall levels to postcore_initcall" that has already been merged. Also note that this patch does not implement clk_set_rate for the PLL, that will be posted later on when available. Cc: Stephen Boyd <sboyd@codeaurora.org> Acked-by:
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- 29 Feb, 2016 1 commit
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Archit Taneja authored
The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading its current value from the NS register. Using the pre-divider wasn't really intended when creating these ops. The pixel RCG was only intended to achieve fractional multiplication provided in the pixel_table array. Leaving the pre-divider to the existing register value results in a wrong pixel clock when the bootloader sets up the display. This was left unidentified because the IFC6410 Plus board on which this was verified didn't have a bootloader that configured the display. Don't set the RCG pre-divider in freq_tbl to the existing NS register value. Force it to 1 and only use the M/N counter to achieve the desired fractional multiplication. Cc: Vinay Simha <vinaysimha@inforcecomputing.com> Signed-off-by:
Archit Taneja <architt@codeaurora.org> Tested-by:
John Stultz <john.stultz@linaro.org> Signed-off-by:
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- 28 Feb, 2016 2 commits
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Lothar Waßmann authored
Add the necessary clock to use the KPP interface on i.MX6UL. Signed-off-by:
Lothar Waßmann <LW@KARO-electronics.de> Acked-by:
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Lothar Waßmann authored
remove whitespace before TAB. Signed-off-by:
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- 27 Feb, 2016 10 commits
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Stephen Boyd authored
Sparse complains here because we dropped the __iomem annotation when casting the aligned address. Add __iomem back so that sparse stops complaining. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: <uclinux-h8-devel@lists.sourceforge.jp> Signed-off-by: -
Stephen Boyd authored
The check for < 0 is impossible now that of_clk_get_parent_count() returns an unsigned int. Simplify the code and update the types. Cc: Hans de Goede <hdegoede@redhat.com> Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Acked-by:
Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: <linux-fbdev@vger.kernel.org> Signed-off-by:
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Stephen Boyd authored
The check for < 0 is impossible now that of_clk_get_parent_count() returns an unsigned int. Simplify the code and update the types. Acked-by:
Felipe Balbi <balbi@kernel.org> Cc: <linux-usb@vger.kernel.org> Signed-off-by:
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Stephen Boyd authored
Change the types here to unsigned int instead of int and update the checks for == 0 instead < 1 to be more explicit about what's going on now that of_clk_get_parent_count() has changed return types. Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: -
Stephen Boyd authored
The return type of of_clk_get_parent_count() is an unsigned int now, so let's update the code here to be more explicit about the range of values we can test for. Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Signed-off-by: -
Stephen Boyd authored
The checks for < 0 are impossible now that of_clk_get_parent_count() returns an unsigned int. Simplify the code and update the types. Cc: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: -
Stephen Boyd authored
The checks for < 1 can be simplified now that of_clk_get_parent_count() returns an unsigned int. Update the code to reflect the int to unsigned int change. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: <uclinux-h8-devel@lists.sourceforge.jp> Signed-off-by: -
Stephen Boyd authored
The check for < 0 is impossible now that of_clk_get_parent_count() returns an unsigned int. Simplify the code and update the type here. Signed-off-by: -
Stephen Boyd authored
These checks for < 0 are impossible now that of_clk_get_parent_count() returns an unsigned int. Change the checks for == 0 and update the type. Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: -
Stephen Boyd authored
Russell King recently pointed out a bug in the clk-gpio code where it fails to register the clk if of_clk_get_parent_count() returns an error because the "clocks" property isn't present in the DT node. If we're trying to count parents from DT we'd like to know the count, not if there is a "clocks" property or not. Furthermore, some drivers are assigning the return value to their clk_init_data::num_parents member which is unsigned, leading to potentially large numbers of parents when the property isn't present. Let's change the API to return an unsigned int instead of an int. All the callers just want to know the count anyway, and this avoids the bug that was in the clk-gpio driver. Signed-off-by:
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- 26 Feb, 2016 3 commits
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Geert Uytterhoeven authored
of_clk_init() uses for_each_matching_node_and_match() to find clock providers, which returns all matching device nodes, whether they are enabled or not. Hence clock providers that are disabled explicitly in DT using e.g. "status = "disabled"; are still activated. Add a check to ignore device nodes that are not enabled, like of_irq_init() does. Reported-by:
Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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Shawn Lin authored
Let's compare the degrees from clk_set_rate with clk->core->phase. If the requested degrees is already there, skip the following steps. Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> [sboyd@codeaurora.org: s/drgrees/degrees/ in commit text] Signed-off-by:
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Martin Sperl authored
Added missing CTRL and DIV clock register definitions for: PCM, SLIM, TCNT, TEC, TD0, TD1 Register information taken from: https://rawgit.com/msperl/rpi-registers/master/rpi-registers.html#CM which extracted the information from the header files shared by Broadcom/rpi foundation in this file: http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gzSigned-off-by:
Martin Sperl <kernel@martin.sperl.org> Reviewed-by:
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- 25 Feb, 2016 3 commits
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Simon Horman authored
As of 9b5ba0df ("ARM: shmobile: Introduce ARCH_RENESAS") all platforms that use Renesas clock drivers now select ARCH_RENESAS. As it is present in drivers/clk/Makefile ARCH_SHMOBILE_MULTI may now be removed. This is part of an ongoing process to migrate from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that RENESAS seems to be a more appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs. Signed-off-by:
Simon Horman <horms+renesas@verge.net.au> Acked-by:
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git://linuxtv.org/snawrocki/samsungStephen Boyd authored
Pull Samsung clk driver changes from Sylwester Nawrocki: Mostly correction of errors in the exynos5433 SoC clocks definition, dropping read-only registers from the suspend/resume register save/restore list and exposition of two clocks required for the exynos5433 HDMI subsystem operation. * tag 'clk-samsung-4.6' of git://linuxtv.org/snawrocki/samsung: clk: samsung: exynos5433: Fix wrong registers of PCLK_GSCL_SMMU clocks clk: samsung: exynos5433: Fix mout_aclk_cam1*_user clocks definition clk: samsung: exynos5433: Drop RO registers from the save/restore lists clk: samsung: exynos5433: Fix definitions of SCLK ISP SENSOR0 clocks clk: samsung: exynos5433: Fix definitions of MUX_SEL_CAM04 clocks clk: samsung: exynos5433: Fix typos in *_ISP_MPWM clock names clk/samsung: exynos5433: add pclk_decon clock clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks
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Kevin Smith authored
The core clock does not depend on corediv, so enabling corediv based on the clock is not really correct. Move the corediv config option from the clock driver Kconfig to the mvebu Kconfig so that it can be enabled by the MACH option instead. This also enables corediv on Armada 375 and 38X, which was previously missing. Signed-off-by:
Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
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