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  1. 24 Jul, 2020 1 commit
  2. 11 Jul, 2020 1 commit
    • Loic Poulain's avatar
      clk: qcom: Add CPU clock driver for msm8996 · 03e342dc
      Loic Poulain authored
      Each of the CPU clusters (Power and Perf) on msm8996 are
      clocked via 2 PLLs, a primary and alternate. There are also
      2 Mux'es, a primary and secondary all connected together
      as shown below
      
                                   +-------+
                    XO             |       |
                +------------------>0      |
                                   |       |
                         PLL/2     | SMUX  +----+
                           +------->1      |    |
                           |       |       |    |
                           |       +-------+    |    +-------+
                           |                    +---->0      |
                           |                         |       |
      +---------------+    |             +----------->1      | CPU clk
      |Primary PLL    +----+ PLL_EARLY   |           |       +------>
      |               +------+-----------+    +------>2 PMUX |
      +---------------+      |                |      |       |
                             |   +------+     |   +-->3      |
                             +--^+  ACD +-----+   |  +-------+
      +---------------+          +------+         |
      |Alt PLL        |                           |
      |               +---------------------------+
      +---------------+         PLL_EARLY
      
      The primary PLL is what drives the CPU clk, except for times
      when we are reprogramming the PLL itself (for rate changes) when
      we temporarily switch to an alternate PLL. A subsequent patch adds
      support to switch between primary and alternate PLL during rate
      changes.
      
      The primary PLL operates on a single VCO range, between 600MHz
      and 3GHz. However the CPUs do support OPPs with frequencies
      between 300MHz and 600MHz. In order to support running the CPUs
      at those frequencies we end up having to lock the PLL at twice
      the rate and drive the CPU clk via the PLL/2 output and SMUX.
      
      So for frequencies above 600MHz we follow the following path
       Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
      and for frequencies between 300MHz and 600MHz we follow
       Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
      
      ACD stands for Adaptive Clock Distribution and is used to
      detect voltage droops.
      Signed-off-by: default avatarRajendra Nayak <rnayak@codeaurora.org>
      Rajendra Nayak: Initial RFC - https://lkml.org/lkml/2016/9/29/84Signed-off-by: default avatarIlia Lin <ilialin@codeaurora.org>
      Ilia Lin:  - reworked clock registering
                 - Added clock-tree diagram
                 - non-builtin support
                 - clock notifier on rate change
                 - https://lkml.org/lkml/2018/5/24/123Signed-off-by: default avatarLoic Poulain <loic.poulain@linaro.org>
      Loic Poulain: - fixed driver remove / clk deregistering
                    - Removed useless memory barriers
                    - devm usage when possible
                    - Fixed Kconfig depends
      
      Link: https://lore.kernel.org/r/1593766185-16346-3-git-send-email-loic.poulain@linaro.orgSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      03e342dc
  3. 22 Jun, 2020 2 commits
  4. 27 May, 2020 1 commit
  5. 26 May, 2020 1 commit
  6. 20 Mar, 2020 1 commit
  7. 09 Mar, 2020 1 commit
  8. 09 Jan, 2020 1 commit
  9. 05 Jan, 2020 3 commits
  10. 24 Dec, 2019 1 commit
  11. 19 Dec, 2019 2 commits
  12. 07 Nov, 2019 3 commits
  13. 08 Aug, 2019 1 commit
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  15. 21 May, 2019 1 commit
  16. 11 Apr, 2019 1 commit
  17. 11 Jan, 2019 1 commit
  18. 10 Dec, 2018 1 commit
    • Stephen Boyd's avatar
      clk: qcom: Move to menuconfig and reduce lines · f071bceb
      Stephen Boyd authored
      We duplicate the 'depends on' in almost every Kconfig here, and it's
      getting out of hand now that we have tens of options for various SoC
      drivers here. Let's clean it up a little by making a menuconfig for a
      submenu and adding an if wrapper around the driver section.
      
      Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
      Cc: Taniya Das <tdas@codeaurora.org>
      Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      f071bceb
  19. 03 Dec, 2018 1 commit
    • Taniya Das's avatar
      clk: qcom: Add lpass clock controller driver for SDM845 · 8d3e5b9c
      Taniya Das authored
      Add support for the lpass clock controller found on SDM845 based devices.
      This would allow lpass peripheral loader drivers to control the clocks to
      bring the subsystem out of reset.
      LPASS clocks present on the global clock controller would be registered
      with the clock framework based on the protected-clock flag. Also do not
      gate these clocks if they are left unused, as the lpass clocks require
      the global clock controller lpass clocks to be enabled before they are
      accessed. Mark the GCC lpass clocks as CRITICAL, for the LPASS clock
      access.
      Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
      Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      8d3e5b9c
  20. 28 Nov, 2018 1 commit
  21. 17 Oct, 2018 4 commits
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  23. 31 Aug, 2018 1 commit
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  26. 01 Jun, 2018 1 commit
  27. 08 May, 2018 1 commit
  28. 17 Apr, 2018 1 commit
  29. 02 Jan, 2018 2 commits