- 01 Dec, 2020 1 commit
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Sergio Paracuellos authored
This driver includes the following two files directly: - mt7621.h - ralink_regs.h Compilation for its related platform properly works because its real path is included in 'arch/mips/ralink/Platform' as cflags. This driver depends on RALINK but also is enabled for COMPILE_TEST where nothing about its platform is known and this directly included files are not found at all breaking compilation. If we want 'COMPILE_TEST' we have to change cflags also inside 'phy/ralink' subdirectory Makefile which seems that does not like to linux-phy maintainers. Hence remove COMPILE_TEST from Kconfig to avoid the problem. Fixes: d87da323 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY") Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20201201112051.17463-2-sergio.paracuellos@gmail.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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- 30 Nov, 2020 12 commits
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Tiezhu Yang authored
devm_ioremap_resource() will be not built in lib/devres.c if CONFIG_HAS_IOMEM is not set, of_address_to_resource() will be not built in drivers/of/address.c if CONFIG_OF_ADDRESS is not set, and then there exists two build errors about undefined reference to "devm_ioremap_resource" and "of_address_to_resource" in phy-mtk-xsphy.c under COMPILE_TEST and CONFIG_PHY_MTK_XSPHY, make PHY_MTK_XSPHY depend on HAS_IOMEM and OF_ADDRESS to fix it. The above issue is reported by kernel test robot <lkp@intel.com>, through the discussion in the v1 patch, as Chunfeng said we need also do this for config PHY_MTK_TPHY: drivers/phy/mediatek/phy-mtk-tphy.c:1157: retval = of_address_to_resource(child_np, 0, &res); drivers/phy/mediatek/phy-mtk-tphy.c:1123: tphy->sif_base = devm_ioremap_resource(dev, sif_res); drivers/phy/mediatek/phy-mtk-tphy.c:1164: instance->port_base = devm_ioremap_resource(&phy->dev, &res); Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Tiezhu Yang <yangtiezhu@loongson.cn> Acked-by:
Randy Dunlap <rdunlap@infradead.org> Acked-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1606289865-692-1-git-send-email-yangtiezhu@loongson.cnSigned-off-by:
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JC Kuo authored
In commit "phy: tegra: xusb: Add usb-phy support", an OTG capable PHY device, such as phy-usb2.0 device of Jetson-TX1 platform, will be bound to the tegra-xusb-padctl driver by the following line in tegra_xusb_setup_usb_role_switch(). port->usb_phy.dev->driver = port->padctl->dev->driver; With this, dev_pm_ops set of tegra-xusb-padctl driver will be invoked for the OTG capable PHY incorrectly as below logs show. This commit fixes the issue by assigning an empty driver to it. [ 153.451108] tegra-xusb-padctl phy-usb2.0: > tegra_xusb_padctl_suspend_noirq(dev=ffff000080917000) [ 153.460353] tegra-xusb-padctl phy-usb2.0: driver: ffff8000114453e0 (tegra_xusb_padctl_driver) [ 153.469245] tegra-xusb-padctl phy-usb2.0: padctl: ffff0000829f6480 [ 153.475772] tegra-xusb-padctl phy-usb2.0: soc: ef7bdd7fffffffff (0xef7bdd7fffffffff) [ 153.484061] Unable to handle kernel paging request at virtual address 007bdd800000004f [ 153.492132] Mem abort info: [ 153.495083] ESR = 0x96000004 [ 153.498308] EC = 0x25: DABT (current EL), IL = 32 bits [ 153.503771] SET = 0, FnV = 0 [ 153.506979] EA = 0, S1PTW = 0 [ 153.510260] Data abort info: [ 153.513200] ISV = 0, ISS = 0x00000004 [ 153.517181] CM = 0, WnR = 0 [ 153.520302] [007bdd800000004f] address between user and kernel address ranges [ 153.527600] Internal error: Oops: 96000004 [#1] PREEMPT SMP [ 153.533231] Modules linked in: nouveau panel_simple tegra_video(C) tegra_drm drm_ttm_helper videobuf2_dma_contig ttm videobuf2_memops cec videobuf2_v4l2 videobuf2_common drm_kms_helper v4l2_fwnode videodev drm mc snd_hda_codec_hdmi cdc_ether usbnet snd_hda_tegra r8152 crct10dif_ce snd_hda_codec snd_hda_core tegra_xudc host1x lp855x_bl at24 ip_tables x_tables ipv6 [ 153.566417] CPU: 0 PID: 300 Comm: systemd-sleep Tainted: G C 5.10.0-rc3-next-20201113-00019-g5c064d5372b0-dirty #624 [ 153.578283] Hardware name: NVIDIA Jetson TX1 Developer Kit (DT) [ 153.584281] pstate: 40000005 (nZcv daif -PAN -UAO -TCO BTYPE=--) [ 153.590381] pc : tegra_xusb_padctl_suspend_noirq+0x88/0x100 [ 153.596016] lr : tegra_xusb_padctl_suspend_noirq+0x80/0x100 [ 153.601632] sp : ffff8000120dbb60 [ 153.604999] x29: ffff8000120dbb60 x28: ffff000080a1df00 [ 153.610430] x27: 0000000000000002 x26: ffff8000106f8540 [ 153.615858] x25: ffff8000113ac4a4 x24: ffff80001148c198 [ 153.621277] x23: ffff800010c4538c x22: 0000000000000002 [ 153.626692] x21: ffff800010ccde80 x20: ffff0000829f6480 [ 153.632107] x19: ffff000080917000 x18: 0000000000000030 [ 153.637521] x17: 0000000000000000 x16: 0000000000000000 [ 153.642933] x15: ffff000080a1e380 x14: 74636461702d6273 [ 153.648346] x13: ffff8000113ad058 x12: 0000000000000f39 [ 153.653759] x11: 0000000000000513 x10: ffff800011405058 [ 153.659176] x9 : 00000000fffff000 x8 : ffff8000113ad058 [ 153.664590] x7 : ffff800011405058 x6 : 0000000000000000 [ 153.670002] x5 : 0000000000000000 x4 : ffff0000fe908bc0 [ 153.675414] x3 : ffff0000fe910228 x2 : 162ef67e0581e700 [ 153.680826] x1 : 162ef67e0581e700 x0 : ef7bdd7fffffffff [ 153.686241] Call trace: [ 153.688769] tegra_xusb_padctl_suspend_noirq+0x88/0x100 [ 153.694077] __device_suspend_noirq+0x68/0x1cc [ 153.698594] dpm_noirq_suspend_devices+0x10c/0x1d0 [ 153.703456] dpm_suspend_noirq+0x28/0xa0 [ 153.707461] suspend_devices_and_enter+0x234/0x4bc [ 153.712314] pm_suspend+0x1e4/0x270 [ 153.715868] state_store+0x8c/0x110 [ 153.719440] kobj_attr_store+0x1c/0x30 [ 153.723259] sysfs_kf_write+0x4c/0x7c [ 153.726981] kernfs_fop_write+0x124/0x240 [ 153.731065] vfs_write+0xe4/0x204 [ 153.734449] ksys_write+0x6c/0x100 [ 153.737925] __arm64_sys_write+0x20/0x30 [ 153.741931] el0_svc_common.constprop.0+0x78/0x1a0 [ 153.746789] do_el0_svc+0x24/0x90 [ 153.750181] el0_sync_handler+0x254/0x260 [ 153.754251] el0_sync+0x174/0x180 [ 153.757663] Code: aa0303e2 94000f64 f9405680 b40000e0 (f9402803) [ 153.763826] ---[ end trace 81543a3394cb409d ]--- Fixes: e8f7d2f4 ("phy: tegra: xusb: Add usb-phy support") Signed-off-by:
JC Kuo <jckuo@nvidia.com> Acked-by:
Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20201117083803.185209-1-jckuo@nvidia.comSigned-off-by:
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Yejune Deng authored
devm_reset_control_array_get_exclusive() looks more readable Signed-off-by:
Yejune Deng <yejune.deng@gmail.com> Reviewed-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by:
Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/1605666995-16462-1-git-send-email-yejune.deng@gmail.comSigned-off-by:
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Neil Armstrong authored
In order to keep OTG ID detection even when in Host mode, the ID line of the PHY (if the current phy is an OTG one) pull-up should be kept enable in both modes. This fixes OTG switch on GXL, GXM & AXG platforms, otherwise once switched to Host, the ID detection doesn't work anymore to switch back to Device. Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Reviewed-by:
Kevin Hilman <khilman@baylibre.com> Reviewed-by:
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Neil Armstrong authored
For consistency, replace DSI_LANE definitions with BIT() macro and remove the unused DSI_LANE_MASK definition. Suggested-by:
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Marek Szyprowski authored
Exynos5420 differs a bit from Exynos5250 in USB2 PHY related registers in the PMU region. Add a variant for the Exynos5420 case. Till now, USB2 PHY worked only because the bootloader enabled the PHY, but then driver messed USB 3.0 DRD related registers during the suspend/resume cycle. Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Acked-by:
Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201120085637.7299-2-m.szyprowski@samsung.comSigned-off-by:
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Sergio Paracuellos authored
Remove this driver from staging because it has been moved into its properly place in the kernel. Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: https://lore.kernel.org/r/20201121155037.21354-5-sergio.paracuellos@gmail.comSigned-off-by:
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Sergio Paracuellos authored
Adding myself as maintainer for mt7621 pci phy driver. Signed-off-by:
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Sergio Paracuellos authored
This patch adds a driver for the PCIe PHY of MT7621 SoC. Signed-off-by:
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Sergio Paracuellos authored
Add bindings to describe Mediatek MT7621 PCIe PHY. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201121155037.21354-2-sergio.paracuellos@gmail.comSigned-off-by:
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Wan Ahmad Zainie authored
Add PHY driver for the USB3.1 and USB 2.0 PHYs found on Intel Keem Bay SoC. This driver takes care of enabling the required USB susbsystem (USS) clocks, initializing the PHYs and turning on/off the USB dwc3 core. Signed-off-by:
Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20201116120831.32641-3-wan.ahmad.zainie.wan.mohamad@intel.comSigned-off-by:
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Wan Ahmad Zainie authored
Binding description for Intel Keem Bay USB PHY. Signed-off-by:
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- 20 Nov, 2020 8 commits
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Vinod Koul authored
Fix the typo s/tunning/tuning Fixes: 496db029 ("phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY") Signed-off-by:
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Jaehoon Chung authored
Exynos5440 SoC support has been dropped since commit 8c83315d ("ARM: dts: exynos: Remove Exynos5440"). Rework this driver to support PCIe PHY variant found in the Exynos5433 SoCs. Signed-off-by:
Jaehoon Chung <jh80.chung@samsung.com> [mszyprow: reworked the driver to support only Exynos5433 variant, rebased onto current kernel code, rewrote commit message] Signed-off-by:
Jingoo Han <jingoohan1@gmail.com> Link: https://lore.kernel.org/r/20201120102627.14450-1-m.szyprowski@samsung.comSigned-off-by:
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Amelie Delaunay authored
Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format using json-schema. Signed-off-by:
Amelie Delaunay <amelie.delaunay@st.com> Reviewed-by:
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Neil Armstrong authored
The AXG Analog MIPI-DSI PHY also provides functions to the PCIe PHY, thus we need to have inclusive support for both interfaces at runtime. This fixes the regmap get from parent node, removes cell param to select a mode and implement runtime configuration & power on/off for both functions since they are not exclusive. Signed-off-by:
Remi Pommarel <repk@triplefau.lt> Link: https://lore.kernel.org/r/20201116101647.73448-4-narmstrong@baylibre.comSigned-off-by:
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Neil Armstrong authored
The Amlogic AXG MIPI + PCIe Analog PHY provides function for both PCIe and MIPI DSI at the same time, and is not exclusive. Thus remove the invalid phy cell parameter. Signed-off-by:
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Neil Armstrong authored
The Amlogic AXG SoCs embeds a MIPI D-PHY used to communicate with DSI panels. Signed-off-by:
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Neil Armstrong authored
The PHY registers happens to be at the beginning of a large zone containing interleaved system registers (mainly clocks, power management, PHY control..), found in all Amlogic SoC so far. The goal is to model it the same way as the other "features" of this zone, like Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt and Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml and have a coherent bindings scheme over the Amlogic SoCs. This update the description, removed the reg attribute then updates the example accordingly. Signed-off-by:
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Neil Armstrong authored
The Amlogic AXg SoCs embeds a MIPI D-PHY to communicate with DSI panels, this adds the bindings. This D-PHY depends on a separate analog PHY. Signed-off-by:
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- 19 Nov, 2020 2 commits
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Rafał Miłecki authored
Initially this PHY driver was implementing MDIO access on its own. It was caused by lack of proper hardware design understanding. It has been changed back in 2017. DT bindings were changed and driver was updated to use MDIO layer. It should be really safe now to drop the old deprecated code. All Linux stored DT files don't use it for 3,5 year. There is close to 0 chance there is any bootloader with its own DTB using old the binding. Signed-off-by:
Rafał Miłecki <rafal@milecki.pl> Acked-by:
Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20201113113423.9466-1-zajec5@gmail.comSigned-off-by:
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Yangtao Li authored
For the current code, enable_pmu_unk1 only works in non-a83t and non-h6 types. So let's delete it from the sun50i_h6_cfg. Signed-off-by:
Yangtao Li <frank@allwinnertech.com> Link: https://lore.kernel.org/r/dc8cbb7b3cd59902a6719f207d18a232903fac8a.1604988979.git.frank@allwinnertech.comSigned-off-by:
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- 17 Nov, 2020 1 commit
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Vinod Koul authored
This reverts commit 3cc8e867 ("phy: amlogic: Replace devm_reset_control_array_get()") as it caused build failure drivers/soc/amlogic/meson-ee-pwrc.c: In function 'meson_ee_pwrc_init_domain': drivers/soc/amlogic/meson-ee-pwrc.c:416:65: error: expected ';' before 'if' Reported-by:
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- 16 Nov, 2020 16 commits
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Jon Hunter authored
Deferred probe is an expected return value for devm_regulator_bulk_get(). Given that the driver deals with it properly, there's no need to output a warning that may potentially confuse users. Signed-off-by:
Jon Hunter <jonathanh@nvidia.com> Acked-by:
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Florian Fainelli authored
Read the 'brcm,tx-amplitude-millivolt' property from Device Tree and propagate its value into the appropriate test transmit register to change the TX amplitude. Signed-off-by:
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Florian Fainelli authored
Document a new property which allows the selection of the SATA AFE TX amplitude in milli Volts. Possible values are 400, 500, 600 and 800mV. Acked-by:
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Amelie Delaunay authored
Change stm32-usbphyc driver to defer its probe when the expected reset control has its probe operation deferred. Signed-off-by:
Etienne Carriere <etienne.carriere@st.com> Signed-off-by:
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Amelie Delaunay authored
Change stm32-usbphyc driver to not print an error message when the device probe operation is deferred. Signed-off-by:
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Rikard Falkeborn authored
The only usage of tegra_xusb_pad_type and tegra_xusb_port_type is to assign their address to the type field in the device struct, which is a const pointer. Make them const to allow the compiler to put them in read-only memory. Signed-off-by:
Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20201109215844.167954-1-rikard.falkeborn@gmail.comSigned-off-by:
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Yejune Deng authored
devm_reset_control_array_get_exclusive() looks more readable Signed-off-by:
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Swapnil Jakhade authored
Add Cadence Sierra PHY bindings in YAML format. Signed-off-by:
Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource(_byname) to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource(_byname) to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource(_byname) to simplify code Signed-off-by:
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