- 06 Feb, 2021 3 commits
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Vinod Koul authored
Add the tables for init sequences for UFS QMP phy found in SM8350 SoC. Signed-off-by:
Vinod Koul <vkoul@kernel.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210204165805.62235-4-vkoul@kernel.orgSigned-off-by:
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Vinod Koul authored
Add the registers for UFS found in SM8350. The UFS phy used in SM8350 seems to have same offsets as V5 phy, although Documentation for that is lacking. Signed-off-by:
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Vinod Koul authored
Add the compatible strings for the UFS PHY found on SM8350 SoC. Signed-off-by:
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- 04 Feb, 2021 7 commits
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Konrad Dybcio authored
This is required to bring up the PHY on MDM9607-based boards. Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210131013124.54484-1-konrad.dybcio@somainline.orgSigned-off-by:
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Baruch Siach authored
This compatible string is for the USB PHY on IPQ60xx systems. Signed-off-by:
Baruch Siach <baruch@tkos.co.il> Link: https://lore.kernel.org/r/7e1e7bda6ccdaab9adeeb956fac1acc39908a8dc.1611756920.git.baruch@tkos.co.ilSigned-off-by:
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Kathiravan T authored
Add the phy init sequence for the Super Speed ports found on IPQ6018. Signed-off-by:
Kathiravan T <kathirav@codeaurora.org> [baruch: add ipq6018_regs_layout[], drop binding change] Signed-off-by:
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Bjorn Andersson authored
The Qualcomm SC8180X has two QMP phys used for SuperSpeed USB, which are either the same or very similar to the same found in SM8150. Add a compatible for this, reusing the existing SM8150 USB phy config. Signed-off-by:
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Bjorn Andersson authored
The UFS phy found in the Qualcomm SC8180X is either the same or very similar to the phy present in SM8150, so add a compatible and reuse the SM8150 configuration. Signed-off-by:
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Bjorn Andersson authored
Add compatibles for the Qualcomm QMP PHY binding for the SuperSpeed USB phys found in the SC8180x platform. Signed-off-by:
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Bjorn Andersson authored
Add compatible for the SC8180x UFS PHY to the QMP binding. Signed-off-by:
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- 19 Jan, 2021 6 commits
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AngeloGioacchino Del Regno authored
Support for the SDM630/660 series of SoCs was added to the driver: document the qcom,sdm660-qusb2-phy compatible here. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by:
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AngeloGioacchino Del Regno authored
The SDM660 SoC uses the same configuration as MSM8996, but the clock scheme uses a differential reference clock and none of the SoCs in this series (630, 636 and others) have got a usable PHY_CLK_SCHEME register in the TCSR for clk scheme detection. Signed-off-by:
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AngeloGioacchino Del Regno authored
The TCSR's PHY_CLK_SCHEME register is not available on all SoC models, but some may still use a differential reference clock. In preparation for these SoCs, add a se_clk_scheme_default configuration entry and declare it to true for all currently supported SoCs (retaining the previous defaults. This patch brings no functional changes. Signed-off-by:
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Jack Pham authored
Add the compatible strings for the USB2 PHYs found on QCOM SM8250 & SM8350 SoCs. Note that the SM8250 compatible is already in use in the dts and driver implementation but was missing from the documentation. Signed-off-by:
Jack Pham <jackp@codeaurora.org> Reviewed-by:
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Jack Pham authored
Add support for the USB DP & UNI PHYs found on SM8350. These use version 5.0.0 of the QMP PHY IP and thus require new "V5" definitions of the register offset macros for the QSERDES RX and TX blocks. The QSERDES common and QPHY PCS blocks' register offsets are largely unchanged from V4 so some of the existing macros can be reused. Signed-off-by:
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Jack Pham authored
Add the compatible strings for the USB3 PHYs found on SM8150, SM8250 and SM8350 SoCs. These require separate subschemas due to the different required clock entries. Note the SM8150 and SM8250 compatibles have already been in place in the dts as well as the driver implementation but were missing from the documentation. Signed-off-by:
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- 17 Jan, 2021 2 commits
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Manivannan Sadhasivam authored
Add support for USB3 QMP PHY found in SDX55 platform. SDX55 uses version 4.0.0 of the QMP PHY IP and doesn't make use of "com_aux" clock. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210111113010.32056-3-manivannan.sadhasivam@linaro.orgSigned-off-by:
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Manivannan Sadhasivam authored
Add devicetree YAML binding for Qualcomm QMP Super Speed (SS) PHY found in SDX55. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210111113010.32056-2-manivannan.sadhasivam@linaro.orgSigned-off-by:
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- 13 Jan, 2021 20 commits
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Amelie Delaunay authored
USBPHYC has a register per phy to control and monitor the debug interface of the HS PHY through a digital debug access. With this register, it is possible to know if PLL Lock input to phy is high. That means the PLL is ready for HS operation. Instead of using an hard-coded delay after PLL enable and PLL disable, use this bit to ensure good operating of the HS PHY. Also use an atomic counter (n_pll_cons) to count the actual number of PLL consumers and get rid of stm32_usbphyc_has_one_phy_active. The boolean active in the usbphyc_phy structure is kept, because we need to know in remove if a phy_exit is required to properly disable the PLL. Signed-off-by:
Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20210105090525.23164-7-amelie.delaunay@foss.st.comSigned-off-by:
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Amelie Delaunay authored
To ensure a good balancing of regulators, and allow PLL disabling when the driver is removed, call stm32_usbphyc_phy_exit on each ports to set phys inactive and disable PLL. Signed-off-by:
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Amelie Delaunay authored
To ensure a good balancing of regulators, force PLL disable either by reset or by clearing the PLLEN bit. If waiting the powerdown pulse delay isn't enough, return -EPROBE_DEFER instead of polling the PLLEN bit, which will be low at the next probe. Signed-off-by:
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Amelie Delaunay authored
Due to async_schedule_domain call in regulator_bulk_enable, scheduling while atomic bug can raise if regulator_bulk_enable is called under atomic context. To avoid this issue, this patch replaces all regulator_bulk* by regulator_ per regulators. Signed-off-by:
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Amelie Delaunay authored
PLL block requires to be powered with 1v1 and 1v8 supplies to catch ENABLE signal. Currently, supplies are managed through phy_ops .power_on/off, and PLL activation/deactivation is managed through phy_ops .init/exit. The sequence of phy_ops .power_on/.phy_init, .power_off/.exit is USB drivers dependent. To ensure a good behavior of the PLL, supplies have to be managed at PLL activation/deactivation. That means the supplies need to be put in usbphyc node and not in phy children nodes. Signed-off-by:
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Amelie Delaunay authored
PLL block requires to be powered with 1v1 and 1v8 supplies to catch ENABLE signal. Currently, supplies are managed through phy_ops .power_on/off, and PLL activation/deactivation is managed through phy_ops .init/exit. The sequence of phy_ops .power_on/.phy_init, .power_off/.exit is USB drivers dependent. To ensure a good behavior of the PLL, supplies have to be managed at PLL activation/deactivation. That means the supplies need to be put in usbphyc parent node and not in phy children nodes. Signed-off-by:
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Mauro Carvalho Chehab authored
Changeset ba2bf1f0 ("dt-bindings: phy: Add Cadence Sierra PHY bindings in YAML format") renamed: Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt to: Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml. Update its cross-reference accordingly. Signed-off-by:
Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/3550b08d4e8312e7d4a247a3515a93a5f0fd04c5.1610535350.git.mchehab+huawei@kernel.orgSigned-off-by:
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Rafał Miłecki authored
BCM4908 seems to have slightly different registers but works when programmed just like the STB one. Signed-off-by:
Rafał Miłecki <rafal@milecki.pl> Acked-by:
Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20210106205838.10964-3-zajec5@gmail.comSigned-off-by:
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Rafał Miłecki authored
BCM4908 uses the same PHY and may require just a slightly different programming. Signed-off-by:
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Rafał Miłecki authored
Changes that require mentioning: 1. interrupt-names Name "wakeup" was changed to the "wake". It matches example and what Linux driver looks for in the first place 2. brcm,ipp and brcm,ioc Both were described as booleans with 0 / 1 values. In examples they were integers and Linux checks for int as well. Both got uint32. 3. Added minimal description Signed-off-by:
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Zou Wei authored
Fix the following sparse warning: drivers/phy/mediatek/phy-mtk-mipi-dsi.c:237:24: warning: symbol 'mtk_mipi_tx_driver' was not declared. Should it be static? Signed-off-by:
Zou Wei <zou_wei@huawei.com> Link: https://lore.kernel.org/r/1610415484-92497-1-git-send-email-zou_wei@huawei.comSigned-off-by:
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Chunfeng Yun authored
Convert MIPI DSI PHY binding to YAML schema mediatek,dsi-phy.yaml Signed-off-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by:
Chun-Kuang Hu <chunkuang.hu@kernel.org> Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org> Cc: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20201225075258.33352-7-chunfeng.yun@mediatek.comSigned-off-by:
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Chunfeng Yun authored
Convert HDMI PHY binding to YAML schema mediatek,hdmi-phy.yaml Signed-off-by:
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Chunfeng Yun authored
Convert phy-mtk-ufs.txt to YAML schema mediatek,ufs-phy.yaml Signed-off-by:
Stanley Chu <stanley.chu@mediatek.com> Cc: Stanley Chu <stanley.chu@mediatek.com> Link: https://lore.kernel.org/r/20201225075258.33352-5-chunfeng.yun@mediatek.comSigned-off-by:
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Chunfeng Yun authored
Convert phy-mtk-tphy.txt to YAML schema mediatek,tphy.yaml Signed-off-by:
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Chunfeng Yun authored
Convert phy-mtk-xsphy.txt to YAML schema mediatek,xsphy.yaml Signed-off-by:
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Paul Cercueil authored
Remove the useless field .version from the private structure, which is set but never read. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Reviewed-by:
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20201223124505.40792-1-paul@crapouillou.netSigned-off-by:
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Dan Carpenter authored
This error path should return -EINVAL, but currently it returns success. Fixes: d09945ea ("phy: cadence-torrent: Check total lane count for all subnodes is within limit") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/X9s7Wxq+b6ls0q7o@mwandaSigned-off-by:
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Rafał Miłecki authored
This is slightly cleaner solution that assures noone assings a wrong function to the pointer. Signed-off-by:
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Rafał Miłecki authored
1. Use of_device_get_match_data() helper to simplify the code 2. Check for NULL as a good practice Signed-off-by:
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- 27 Dec, 2020 2 commits
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Linus Torvalds authored
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Linus Torvalds authored
Since commit 36e2c742 ("fs: don't allow splice read/write without explicit ops") we've required that file operation structures explicitly enable splice support, rather than falling back to the default handlers. Most /proc files use the indirect 'struct proc_ops' to describe their file operations, and were fixed up to support splice earlier in commits 40be821d..b24c30c6, but the mountinfo files interact with the VFS directly using their own 'struct file_operations' and got missed as a result. This adds the necessary support for splice to work for /proc/*/mountinfo and friends. Reported-by:
Joan Bruguera Micó <joanbrugueram@gmail.com> Reported-by:
Jussi Kivilinna <jussi.kivilinna@iki.fi> Link: https://bugzilla.kernel.org/show_bug.cgi?id=209971 Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Christoph Hellwig <hch@lst.de> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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