- 29 Aug, 2022 40 commits
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Sonny Jiang authored
This enable VCN PG, CG, DPG and JPEG PG, CG Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Hawking Zhang authored
init cp/pg_flags and extenal_rev_id Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Frank Min <Frank.Min@amd.com> Signed-off-by:
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Hawking Zhang authored
driver doesn't need to program any gc 11_0_0 golden Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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Jinpeng Cui authored
Return value from kfd_wait_on_events() and io_remap_pfn_range() directly instead of taking this in another redundant variable. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Jinpeng Cui <cui.jinpeng2@zte.com.cn> Signed-off-by:
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Jinpeng Cui authored
Return value from expression directly instead of taking this in another redundant variable. Reported-by:
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Martin Tsai authored
[Why] Incorrect cursor position will induce system hang on pipe split. [How] 1.Handle horizontal mirror on rotation, 2.Correct cursor set on piep split. Reviewed-by:
Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by:
Brian Chang <Brian.Chang@amd.com> Signed-off-by:
Martin Tsai <martin.tsai@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Vladimir Stempen authored
[Why] On secondary display hotplug we switch primary stream from ODM2to1 to ODMBypass mode. Current logic will trigger disabling front end for this stream. [How] We need to check if prev_odm_pipe is equal to NULL in order to disable dangling planes in this scenario. Reviewed-by:
Vladimir Stempen <vladimir.stempen@amd.com> Tested-by:
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Ethan Wellenreiter authored
[WHY] Function wasn't returning false when it had a no stream [HOW] Made it return false when it had no stream. Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
Ethan Wellenreiter <Ethan.Wellenreiter@amd.com> Tested-by:
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Ethan Wellenreiter authored
[Why] Pipes get merged in preparation for SubVP but if they don't get used, and are in ODM or some other multi pipe config, it would calculate the voltage level with a viewport of just one pipe from when they were split resulting in too low of a voltage level. [How] Made it so that the viewport and other timing settings get rebuilt and re- initialized after the pipe merge, before calculating the voltage level so it would calculate it correctly. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Aurabindo Pillai authored
[Why&How] plane and stream variables used for cursor size allocation calculation were stale from previous iteration. Redo the iteration to find the correct cursor plane for the calculation. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Alex Sierra authored
[Why] Devices with CPU XGMI iolink do not support PCIe peer access. Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Aric Cyr authored
Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Evan Quan authored
To suppress the warning about version mismatch with the latest 78.54.0 PMFW. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Evan Quan authored
For those SMU13.0.7 unsecure SKUs, the vbios carried pptable is ready to go. Use that one instead of hardcoded softpptable. Signed-off-by:
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Evan Quan authored
For some SMU13.0.0 SKUs, the vbios carried pptable is ready to go. Use that one instead of hardcoded softpptable. Signed-off-by:
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Leo (Hanghong) Ma authored
[Why && How] We would like to have visual confirm color support for SubVP. 1. Set visual confirm color to red: SubVP is enable on this display; 2. Set visual confirm color to green: SubVP is enable on other display and DRR is on this display; 3. Set visual confirm color to blue: SubVP is enable on other display and DRR is off on this display; Reviewed-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Tested-by:
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Anthony Koo authored
- Fix comment to indicate correct visual confirm option Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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Ian Chen authored
Reviewed-by:
Dennis Chan <dennis.chan@amd.com> Acked-by:
Ian Chen <ian.chen@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why & How] This reverts commit e6cf22ef since it causes a SubVP related regression: "Switching between windowed video and fullscreen can intermittently cause black screen" Fixes: e6cf22ef ("drm/amd/display: program k1/k2 divider for virtual signal for DCN32") Reviewed-by:
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Iswara Nagulendran authored
[HOW&WHY] EDP link detection must be updated to support a primary EDP with a link index of greater than 0. * SWDEV-342936 - dc: DSC bringup for SAG 1.5 [WHY] SmartAccess Graphics 1.5 (a.k.a SmartMux 1.5) requires seamless switching between GPUs with DSC enabled. [HOW] Moved DSC programming to apply_single_control_ctx_to_hw before the stream enablement logic to ensure the CRC checker provides valid values for non-black frames allowing the system to come out of forced PSR on d2i. Added additional logic to both generate a black frame through setVisibility calls and keep track of the CRCs values for this black frame when coming out of forced PSR. Updating logic for DalRegKey_DisableDSC to disable DSC on EDP and all ports for systems. [CLEANED] dc: Moved DSC programming to before stream enablement [HOW&WHY] Moved DSC programming to apply_single_control_ctx_to_hw before the stream enablement logic. Co-authored-by:
sregolui <sregolui@amd.com> Reviewed-by:
Jayendran Ramani <Jayendran.Ramani@amd.com> Reviewed-by:
Harry Vanzylldejong <Harry.Vanzylldejong@amd.com> Acked-by:
Iswara Nagulendran <Iswara.Nagulendran@amd.com> Tested-by:
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Charlene Liu authored
[why] fw version check was for release branch. for staging, it has a chance to enter wrong code path. Reviewed-by:
Hansen Dsouza <hansen.dsouza@amd.com> Acked-by:
Charlene Liu <Charlene.Liu@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why&How] When calculating allocation for cursor size, get the real cursor through the HUBP instead of using the maximum cursor size for more optimal allocation Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Aurabindo Pillai authored
[Why&How] When using a 4k monitor when cursor caching is not supported due to framebuffer being on an uncacheable address, enabling display refresh from MALL would trigger corruption if SS is enabled. Prevent entering SS if we are on the edge case and cursor caching is not possible. Do this only if cursor size larger than a 64x64@4bpp. Pull the cursor size calculation out of if condition since cursor address may not be set on all platforms Reviewed-by:
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Aurabindo Pillai authored
For calculating cursor size allocation, surface size was used, resulting in over allocation Reviewed-by:
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Leo Chen authored
[Why & How] Number of encoder is set to 4 but only 3 instances are created. Reviewed-by:
Leo Chen <sancchen@amd.com> Tested-by:
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Ian Chen authored
Refactor edp dsc codes. We split out edp dsc config from "global" to "per-panel" config settings. Reviewed-by:
Mike Hsieh <mike.hsieh@amd.com> Acked-by:
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Alvin Lee authored
[Description] For SubVP scaling case we have to combine the plane scaling and stream scaling. Use UCLK dummy p-state WM for FCLK WM set C [Description] For DCN32/321 program dummy UCLK P-state watermark into FCLK watermark set C register. Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
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Leo (Hanghong) Ma authored
[Why] We want to get the visual confirm color of the bottom-most pipe for test automation. [How] Save the visual confirm color to plane_state before program to MPC; Reviewed-by:
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Taimur Hassan authored
[Why & How] In some cases, there are calls to transition from TX_ON to TX_ON, such as when using MST or during resolution change. This is expected, so allow HW programming to continue. Reviewed-by:
Taimur Hassan <Syed.Hassan@amd.com> Tested-by:
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Gabe Teeger authored
[Why] enable_sw_cntl_psr flag is not needed. For PSR1 and PSR2, we should be passing dirty rectangle and cursor updates to FW regardless of enable_sw_cntl_psr flag. [How] Remove enable_sw_cntl_psr flag from driver. Send cursor info and dirty rectagle status to dmub only in the case of dcn31 and above. Reviewed-by:
Robin Chen <robin.chen@amd.com> Acked-by:
Gabe Teeger <gabe.teeger@amd.com> Tested-by:
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Gabe Teeger authored
[Why] On edp with psr1, we do not provide updates of the cursor position regularly to firmware like with PSR2. To send updates regularly, the flag enable_sw_cntl_psr has to equal 1, but cursor update should be provided regularly to FW regardless of that flag. [How] Ensure that we always send cursor updates to firmware when PSR version equals 1. Reviewed-by:
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Michael Strauss authored
[WHY] Useful for external teams debugging LTTPR issues Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Leo Chen authored
[Why & How] Add a override flag as wa for some specific dongle Co-authored-by:
Leo Chen <SanChuan.Chen@amd.com> Tested-by:
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Alvin Lee authored
[Description] We only want to commit the SubVP config to DMCUB after the main and phantom pipe programming has completed. Commiting the state early can cause issues such as P-State being allowed by the HW early which causes the SubVP state machine to go into a bad state Reviewed-by:
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Taimur Hassan authored
[Why & How] In some cases, there are calls to transition from TX_ON to TX_ON. This is expected, so do not assert. However, these are redundant, so return prematurely. Reviewed-by:
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Wang Fudong authored
[Why] DIG_FIFO_ERROR = 1 caused mst daisy chain 2nd monitor black. [How] We need to set dig fifo read start level = 7 before dig fifo reset during dig fifo enable according to hardware designer's suggestion. If it is zero, it will cause underflow or overflow and DIG_FIFO_ERROR = 1. Reviewed-by:
Wang Fudong <Fudong.Wang@amd.com> Tested-by:
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YuBiao Wang authored
[Why] In amdgpu_cs_ioctl, amdgpu_job_free could be performed ealier if there is -ERESTARTSYS error. In this case, job->hw_fence could be not initialized yet. Putting hw_fence during amdgpu_job_free could lead to a use-after-free warning. [How] Check if drm_sched_job_init is performed before job_free by checking s_fence. v2: Check hw_fence.ops instead since it could be NULL if fence is not initialized. Reverse the condition since !=NULL check is discouraged in kernel. Signed-off-by:
YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Duncan Ma authored
[Why] When ODM is enabled, H timing control register reset to 0. Div mode manual field get overwritten causing no display on certain modes for dcn314. [How] Use REG_UPDATE instead of REG_SET to set div_mode field. Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Tested-by:
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Lewis Huang authored
[Why] LTTPR caps will read fail if aux channel is not active. [How] 1.Perform 600 read upto 10 retry with 1ms delay in between. 2.If fail, return false and trigger another retry detection. 3.If pass, read LTTPR caps in retrieve link caps. Reviewed-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Acked-by:
Lewis Huang <Lewis.Huang@amd.com> Tested-by:
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George Shen authored
[Why] Each index in the DPSTREAMCLK_CNTL register phyiscally maps 1-to-1 with HPO stream encoder instance. On the other hand, each index in DTBCLK_P_CNTL physically maps 1-to-1 with OTG instance. Current DCN32 DPSTREAMCLK_CLK programing assumes that OTG instance always maps 1-to-1 with HPO stream encoder instance. This is not always guaranteed and can result in blackscreen. [How] Program the correct dpstreamclk instance with the correct dtbclk_p source. Reviewed-by:
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