- 09 Jun, 2017 7 commits
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Alex Xie authored
Signed-off-by:
Alex Xie <AlexBin.Xie@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Alex Xie authored
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Alex Xie authored
There are two identical function prototypes in same header file Signed-off-by:
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Harish Kasiviswanathan authored
v2: Fix logical mistake. If CPU update failed amdgpu_vm_bo_update_mapping() would not return and instead fall through to SDMA update. Minor change due to amdgpu_vm_bo_wait() prototype change Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Harish Kasiviswanathan authored
If amdgpu.vm_update_context param is set to use CPU, then Page Directories will be updated by CPU instead of SDMA v2: Call amdgpu_vm_bo_wait before updating the page tables to ensure the PD/PT BOs are free v3: Minor changes - due to amdgpu_vm_bo_wait() prototype change, local variable declaration order and function comments. Signed-off-by:
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Harish Kasiviswanathan authored
v2: Add intr option Helper function useful for CPU update of VM page tables. Also useful if kernel have to synchronously wait till VM page tables are updated. Signed-off-by:
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Harish Kasiviswanathan authored
Add VM update mode module param (amdgpu.vm_update_mode) that can used to control how VM pde/pte are updated for Graphics and Compute. BIT0 controls Graphics and BIT1 Compute. BIT0 [= 0] Graphics updated by SDMA [= 1] by CPU BIT1 [= 0] Compute updated by SDMA [= 1] by CPU By default, only for large BAR system vm_update_mode = 2, indicating that Graphics VMs will be updated via SDMA and Compute VMs will be updated via CPU. And for all all other systems (by default) vm_update_mode = 0 Signed-off-by:
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- 08 Jun, 2017 8 commits
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Alex Deucher authored
Open code them so we can adjust the order in the driver more easily. Reviewed-by:
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Alex Deucher authored
Rather than calling the deprecated drm_pci_init() and drm_pci_exit() which just wrapped the pci functions anyway. Reviewed-by:
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Michel Dänzer authored
Even if CONFIG_DRM_AMDGPU_CIK is enabled. There is no feature parity yet for CIK, in particular amdgpu doesn't support HDMI/DisplayPort audio without DC. v2: * Clarify the lack of feature parity being related to HDMI/DP audio. * Fix "SI" typo in DRM_AMDGPU_CIK help entry. Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com>
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Michel Dänzer authored
This will allow amdgpu-pro / other out-of-tree amdgpu builds to make use of these options for using the out-of-tree amdgpu driver instead of the in-tree radeon driver in a clean way. Reviewed-by:
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Felix Kuehling authored
Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
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Felix Kuehling authored
If AMDGPU supports SI, add a module parameter to control SI support. It's off by default in AMDGPU as long as SI suppost is experimental, while it is on by default in radeon. Signed-off-by:
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Felix Kuehling authored
If AMDGPU supports SI, add a module parameter to control SI support in radeon. It's on by default in radeon, while it will be off by default in AMDGPU as long as SI support is experimental. Signed-off-by:
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Felix Kuehling authored
If AMDGPU supports CIK, add a module parameter to control CIK support. It's on by default in AMDGPU, while it is off by default in radeon. Signed-off-by:
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- 07 Jun, 2017 11 commits
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Alex Deucher authored
It was duplicated across multiple generations. Reviewed-by:
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Alex Deucher authored
This will allow us to share more mec code. Reviewed-by:
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Alex Deucher authored
Lots more common stuff. Reviewed-by:
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Alex Deucher authored
They are gfx related, not general helpers. Reviewed-by:
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Alex Deucher authored
This overrode what queue was actually assigned for kiq. Reviewed-by:
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Alex Deucher authored
Make it consistent. Reviewed-by:
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Alex Deucher authored
This was missed when Andres' queue patches were rebased. Fixes: 42794b27 (drm/amdgpu: take ownership of per-pipe configuration v3) Reviewed-by:
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Alex Deucher authored
Same function was duplicated in all gfx IP files. Reviewed-by:
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Alex Deucher authored
Fixes hangs on single MEC asics. Fixes: 2ed286fb434 (drm/amdgpu: new queue policy, take first 2 queues of each pipe v2) Reviewed-by:
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Alex Deucher authored
The same function was duplicated in all the gfx IPs. Use a single implementation for all. v2: use static inline (Alex Xie) Reviewed-by:
Andres Rodriguez <andresx7@gmail.com> Signed-off-by:
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Alex Deucher authored
Always use the max for the family rather than the per sku limits. This makes sure the mask is always the max size to avoid reporting the wrong number of CUs. Reviewed-by:
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- 06 Jun, 2017 14 commits
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Alex Deucher authored
This was missing for gfx6. Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Alex Deucher authored
Instead of taking the first pipe and giving the rest to kfd, take the first 2 queues of each pipe. Effectively, amdgpu and amdkfd own the same number of queues. But because the queues are spread over multiple pipes the hardware will be able to better handle concurrent compute workloads. amdgpu goes from 1 pipe to 4 pipes, i.e. from 1 compute threads to 4 amdkfd goes from 3 pipe to 4 pipes, i.e. from 3 compute threads to 4 gfx9 was missed when this patch set was rebased to include gfx9. Acked-by:
Tom St Denis <tom.stdenis@amd.com> Acked-by:
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Alex Deucher authored
Pipes provide better concurrency than queues, therefore we want to make sure that apps use queues from different pipes whenever possible. Optimize for the trivial case where an app will consume rings in order, therefore we don't want adjacent rings to belong to the same pipe. gfx9 was missed when these patches were rebased. Reviewed-by:
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Hawking Zhang authored
vddc_dep_on_dal_pwrl is allocated and initialized in cz_hwmgr_backend_init Thus free the memory in cz_hwmgr_backend_fini Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Hawking Zhang authored
vddc_dep_on_dal_pwrl and vq_budgeting_table are allocated and initialized in rv_hwmgr_backend_init. Thus free the memory in rv_hwmgr_backend_fini Signed-off-by:
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Eric Huang authored
For overclocking sclk and mclk. Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by:
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Rex Zhu authored
As the min clk may be large than boot level can support. in this case, just ignore the min clk. Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
Something writes over the first 8 MB so reserve this on vega10 until we root cause it. Signed-off-by:
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Huang Rui authored
User is able to follow the ip block number to write the ip_block_mask for selecting the one which user would like to enable. Signed-off-by:
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Huang Rui authored
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Huang Rui authored
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