- 29 Sep, 2022 40 commits
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Tao Zhou authored
Update umc error address query interface, the mca address can be read from register or input from parameter. TODO: define a common address conversion function to simplify the code. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tao Zhou authored
Make it global so we can convert specific mca address. v2: rename query_error_address_per_channel to convert_ras_error_address Signed-off-by:
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Likun Gao authored
Fix init SDMA microcode error for sdma v4, which caused by mistake when rearch sdma init microcode function (coding 4.2.2 to 4.2.0). Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Hamza Mahfooz authored
Address the following error: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c: In function ‘dc_stream_remove_writeback’: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:527:55: error: array subscript [0, 0] is outside array bounds of ‘struct dc_writeback_info[1]’ [-Werror=array-bounds] 527 | stream->writeback_info[j] = stream->writeback_info[i]; | ~~~~~~~~~~~~~~~~~~~~~~^~~ In file included from ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc.h:1269, from ./drivers/gpu/drm/amd/amdgpu/../display/dc/inc/core_types.h:29, from ./drivers/gpu/drm/amd/amdgpu/../display/dc/basics/dc_common.h:29, from drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:27: ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_stream.h:241:34: note: while referencing ‘writeback_info’ 241 | struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; | Currently, we aren't checking to see if j remains within writeback_info[]'s bounds. So, add a check to make sure that we aren't overflowing the buffer. Reviewed-by:Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Bokun Zhang authored
- Under SRIOV, we need to send REQ_GPU_FINI to the hypervisor during the suspend time. Furthermore, we cannot request a mode 1 reset under SRIOV as VF. Therefore, we will skip it as it is called in suspend_noirq() function. - In the resume code path, we need to send REQ_GPU_INIT to the hypervisor and also resume PSP IP block under SRIOV. Signed-off-by:
Bokun Zhang <Bokun.Zhang@amd.com> Reviewed-by:
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Likun Gao authored
Change the type of parameter on amdgpu_gfx_cp_init_microcode to fix compiler warning. Signed-off-by:
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Asher Song authored
This patch is used to fix following compiling error that occurs in some old kernels. error: ‘for’ loop initial declarations are only allowed in C99 mode for (int i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { Signed-off-by:Asher Song <Asher.Song@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Hawking Zhang authored
To allow upload the list via psp Signed-off-by:
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Jiadong.Zhu authored
The function amdgpu_fence_count_emitted used in work_hander should not call amdgpu_fence_process which must be used in irq handler. Reviewed-by:
Jiadong.Zhu <Jiadong.Zhu@amd.com> Signed-off-by:
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Jiadong.Zhu authored
The current position calulated in gfx_v9_0_ring_emit_patch_cond_exec underflows when the wptr is divisible by ring->buf_mask + 1. Reviewed-by:
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Michael Strauss authored
[WHY] Previously, LTTPR mode was decided during detection which makes link training inflexible as mode can't be dynamically changed. [HOW] -Remove lttpr_mode from link struct, and move to link training settings -Defer choosing LTTPR mode until link training Other DP changes included: -Only use fixed vs/pe link training sequence for 8b/10b encoding -Restrict fixed vs aux timeout workaround to Yellow Carp family Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - LTTPR mode can be be dynamically changed - fixes divide by zero error - features able to use same interface to update cursor info - fixes for llvm compilation issues - Fixes DIO FIFO underflow and other FIFO errors - Partially valid EDIDs handled properly - Phatom pipes are skipped when checking pending flip - Fixed audio on audio on display after unplugging Acked-by:Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why&How] Incorrect variable was being checked for zero condition. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
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Alvin Lee authored
We only gain a benefit of using the ODM2:1 dynamic policy if it allow us to decrease DISPCLK to use the VMIN freq. If the display config can already achieve VMIN DISPCLK freq without ODM2:1, don't apply the policy. Signed-off-by:
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Dillon Varone authored
[Why&How] Several transitions were fixed that will allow Dynamic ODM and MPO transitions to be supported on DCN32. 1) Due to resource limitations, in certain scenarios that require an MPO plane to be split, the features cannot be combined with the current policy. This is due to unsafe transitions being required (OPP instance per MPCC being switched on active pipe is not supported by DCN), to support the split plane with ODM active as it moves across the viewport. Dynamic ODM will now be disabled when MPO is required. 2) When exiting MPO and re-entering ODM, DC assigns an inactive pipe for the next ODM pipe, which under previous power gating policy would result in programming a gated DSC HW block. New policy dynamically gates/un-gates DSC blocks when Dynamic ODM is active to support transitions on DCN32 only. 3) Entry and exit from 3 plane MPO and Dynamic ODM requires a minimal transition so that all pipes which require their MPCC OPP instance to be changed have a full frame to be disabled before reprogramming. To solve this, the Dynamic ODM policy now utilizes minimal state transitions when entering or exiting 3 plane scenarios. 4) Various fixes to DCN32 pipe merge/split algorithm to support Dynamic ODM and MPO transitions. In summary, this commit fixes various transitions to support ODM->MPO and MPO->ODM. Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Dillon Varone <Dillon.Varone@amd.com> Tested-by:
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Wenjing Liu authored
[why] vid stream control is double bufferred, if we don't wait for video stream enable set to 0, we may get temporary image corruption showing on the stream when setting PIXEL_TO_SYMBOL_FIFO_ENABLE to 0. Reviewed-by:
Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Alvin Lee authored
[Description] Accidentally added when should have subtracted in calculation Reviewed-by:
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Aurabindo Pillai authored
[Why&How] Phantom pipes are not programmed fully to hardware and hence we should not expect a flip completion. Reviewed-by:
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Alvin Lee authored
[Description] Update MALL SS NumWays calculation according to programming guide. Reviewed-by:
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Aurabindo Pillai authored
[Why&How] Phantom pipes are not programmed fully to hardware and hence we should not expect a flip completion. Reviewed-by:
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Samson Tam authored
[Why] For individual feature testing, PMFW may not report all clock values back. Driver will default them to 0 but this will cause the BB table to be skipped and default to one state with max clocks. [How] Add helper function to scan through initial clock values and populate them with default clock limits so that BB table can be built. Add dpm_enabled flag to check when DPM is not enabled and to trigger helper function. Reviewed-by:
Samson Tam <samson.tam@amd.com> Tested-by:
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Max Tseng authored
Dc: cursor info update: phase 1: [Why] Different feature might need to update cursor info, but With different approaches. To unify this diversity problem, all features should use The same interface to update cursor. Reviewed-by:
Reza Amini <reza.amini@amd.com> Acked-by:
Max Tseng <max.tseng@amd.com> Tested-by:
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Taimur Hassan authored
[Why] Programming pixel rate divider when FIFO is enabled can cause FIFO error. [How] Skip divider programming when divider values are the same to prevent FIFO error. Reviewed-by:
Taimur Hassan <Syed.Hassan@amd.com> Tested-by:
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Eric Bernstein authored
Remove assert that will hit during odm transition case, since this is a valid case. Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by:
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Ian Chen authored
Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Acked-by:
Ian Chen <ian.chen@amd.com> Tested-by:
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Alvin Lee authored
[Description] - Don't use MALL buffering of any kind when the surface is TMZ - Workaround for a HW bug Reviewed-by:
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Taimur Hassan authored
[Why & How] Some FIFO errors still occur due to reading wrong pixel rate divider. Fix typo to prevent FIFO error. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Charlene Liu authored
[why] adding debug keys used for compliance test. Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
Charlene Liu <Charlene.Liu@amd.com> Tested-by:
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Aric Cyr authored
Revert "dc: skip audio setup when audio stream is enabled" This reverts commit 65fbfb02 [why] We have minimal pipe split transition method to avoid pipe allocation outage.However, this method will invoke audio setup which cause audio output stuck once pipe reallocate. [how] skip audio setup for pipelines which audio stream has been enabled Reviewed-by:
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Wenjing Liu authored
[why] There is a coding error for a missing null check for stream pointer when iterating through pipe_ctx. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] We rely on DMCUB to do this when disabling the link but it should actually come before we disable the DP VID stream. If we don't then the FIFO can end up with underflow that persists the next time it's enabled. [How] Add a DCN314 specific blank sequence that will disable the DIG FIFO first. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] The DIO FIFO will underflow if we turn off the OTG before we turn off the FIFO. Since this happens as part of the OTG workaround and we don't reset the FIFO afterwards we see the error persist. [How] Add disable FIFO before the disable CRTC and enable FIFO after enabling the CRTC. Reviewed-by:
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Brandon Syu authored
[Description] - Have option to exit idle opt on cursor updates for debug and optimizations purposes Reviewed-by:
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Ilya Bakoulin authored
[Why] Partially valid EDIDs on MST sinks are treated the same way as broken EDIDs or read failures and result in a fallback EDID being used instead. [How] If edid_status is EDID_PARTIAL_VALID, prefer to use the valid EDID blocks instead of using a fallback EDID. Reviewed-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] Avoids a race condition where DIO FIFO can underflow due to no incoming data available. [How] Shift the FIFO enable below stream enable. Make sure fullness level is written before the DIO reset takes place and that we're not doing it twice. Reviewed-by:
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Aric Cyr authored
[why] Only a single VLINE interrupt is available so interface should not expose the second one which is used by DMU firmware. [how] Remove references to periodic_interrupt1 and VLINE1 from DC interfaces. Reviewed-by:
Jaehyun Chung <jaehyun.chung@amd.com> Acked-by:
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Alvin Lee authored
[Description] Update to new SR latencies for DCN32 Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by:
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Taimur Hassan authored
[Why] Programming pixel rate divider when FIFO is enabled can cause FIFO error. [How] Skip divider programming when divider values are the same to prevent FIFO error. Reviewed-by:
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Graham Sider authored
Shader wave interrupts were getting dropped in event_interrupt_wq_v11 if the PRIV bit was set to 1. This would often lead to a hang. Until debugger logic is upstreamed, expand comment to stop early return. Signed-off-by:
Graham Sider <Graham.Sider@amd.com> Reviewed-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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Graham Sider authored
Update mes_v11_api_def.h add_queue API with is_aql_queue parameter. Also re-use gds_size for the queue size (unused for KFD). MES requires the queue size in order to compute the actual wptr offset within the queue RB since it increases monotonically for AQL queues. v2: Make is_aql_queue assign clearer Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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