- 07 Jun, 2013 32 commits
-
-
Simon Horman authored
The board has 3 LEDs connected to GPIOs. Add a led-gpio device to support them. Based on "ARM: shmobile: marzen: Add GPIO LEDs" by Laurent Pinchart. Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Kuninori Morimoto authored
SMSC driver will try to get regulator if .config had CONFIG_REGULATOR, and, shmobile_defconfig has it. SMSC driver on Bock-W board will be failed if it doens't have dummy regulator settings. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Kuninori Morimoto authored
Debug serial (= SCIF0) is connected to CN9 upper side, and it is shared by RCAN. This patch adds SCIF/RCAN dipswitch explanation on comment area for developers. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Guennadi Liakhovetski authored
KZM9G uses an AS3711 PMIC to supply power to the CPU and the LCD backlight. The PMIC on the board is pre-programmed to supply correct voltages to the CPU, power supply to the backlight has to be turned on at run-time. The latter is currently performed by a hard-coded I2C command sequence in the board file. This patch removes the backlight hack and instead adds an I2C device to instantiate the AS3711 MFD driver, which will add a regulator device to dynamically adjust CPU voltages and a backlight device. Signed-off-by:
Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Simon Horman authored
As the kzm9d only has one smsc911x device it may be registered as a platform device with id -1. This allows the kzm9d board to access the smsc911x device when CONFIG_REGULATOR (and CONFIG_REGULATOR_FIXED_VOLTAGE) are set. The motivation for which is twofold: using regulators seems to be generally a good thing; it will move the kzm9d defconfig one step closer to being able to be consolidated with other shmobile defconfigs. An alternate but so far untested approach would be to update the definition of dummy_supplies in board-kzm9d.c to use "smsc911x.0" instead of "smsc911x". Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Kuninori Morimoto authored
Bock-W board will needs more board specific ioremap() method. This patch tidyup current FPGA specific settings Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Kuninori Morimoto authored
The orignal commit 3263e09d287fbaa8a9424b5e69396599a3bbd518 (ARM: shmobile: Initial r8a73a4 SoC support V3) put MP clock parent as EXTAL2, but its code was removed on DIV6 clock support commit. This patch makes it consistent. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Simon Horman authored
Conflicts: arch/arm/mach-shmobile/Kconfig arch/arm/mach-shmobile/include/mach/r8a7778.h arch/arm/mach-shmobile/setup-r8a7778.c
-
Guennadi Liakhovetski authored
According to the datasheet, it is not allowed to change div4 clock rates if an earlier rate change operation is still in progress, as indicated by a set kick bit. Signed-off-by:
Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Guennadi Liakhovetski authored
An earlier commit "ARM: shmobile: sh73a0: add support for adjusting CPU frequency" intended to replace some clock operations only for the Z-clock, instead it replaced them for all div4 clocks, since all div4 clocks share the same copy of clock operations. Fix this by using a separate clock operations structure for Z-clock. Signed-off-by:
Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Magnus Damm authored
Break out the function sh73a0_init_delay() that now gets called both for the C version of the code and the DT -reference boards. This way we handle both cases in the same way. Allows us to boot with TWD only in the kernel configuration for C board code. TWD is not yet enabled in the case of DT -reference - this due to a dependency on CCF. Signed-off-by:
Magnus Damm <damm@opensource.se> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Guennadi Liakhovetski authored
This patch enables the use of the generic cpufreq-cpu0 driver on sh73a0. Providing a regulator, a list of OPPs in DT, combined with a virtual cpufreq-cpu0 platform device and a clock, attached to it is everything, the cpufreq-cpu0 driver needs. The first sh73a0 platform, implementing such CPUFreq support is kzm9g-reference. Signed-off-by:
Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Guennadi Liakhovetski authored
On SH73A0 the output of PLL0 is supplied to two dividers, feeding clock to the CPU core and SGX. Lower CPU frequencies allow the use of lower supply voltages and thus reduce power consumption. Signed-off-by:
Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Laurent Pinchart authored
Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Laurent Pinchart authored
Both clock-r8a7740.c and clock-r8a7790.c define a div4_clks array as non-static. Compiling support for both SoCs thus result in a symbol redefinition. Fix it by defining the arrays as static. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Kuninori Morimoto authored
DIV6 clocks control SD*/MMC* core clocks. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Kuninori Morimoto authored
DIV4 clocks control SD* core clocks. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Kuninori Morimoto authored
Almost all clock needs main clock which is basis clock on r8a7790. This patch adds it, and, set its parent/ratio via MD pin. It is based on v0.05 datasheet Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Kuninori Morimoto authored
This patch adds SDHI register function which needs id number (= 0/1/2) Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Kuninori Morimoto authored
Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Kuninori Morimoto authored
R-Car M1 has many clocks, and it is possible to read/use clock ratio of these clocks from FRQMRx. But, these ratio are fixed value and these are decided by MD pin status. This patch reads MD pin status, and used fixed ratio clock for other clocks. It was tesed on bock-w board. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Phil Edworthy authored
Signed-off-by:
Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Kuninori Morimoto authored
DIV6 clocks control each core clocks. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Kuninori Morimoto authored
DIV4 clocks control each core clocks. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Kuninori Morimoto authored
PLL clocks are basis clock for other clock. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Kuninori Morimoto authored
Almost all clock needs main clock which is basis clock on r8a73a4. This patch adds it, and, set parent clock via CKSCR register. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Laurent Pinchart authored
Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by:
Simon Horman <horms@verge.net.au> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Bastian Hecht authored
Add clock association for i2c0 and i2c1 for the new DT names. Signed-off-by:
Bastian Hecht <hechtb+renesas@gmail.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Bastian Hecht authored
When we use the ethernet device via DT setup, we need to add it to a lookup list until this is properly handled later in a DT-only fashion. Signed-off-by:
Bastian Hecht <hechtb+renesas@gmail.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Kuninori Morimoto authored
Ether setup code position was scattering. This patch fixes it up Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Kuninori Morimoto authored
SH_CLK_SET_RATIO() will be trouble without this patch Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Kuninori Morimoto authored
Acked-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
- 06 Jun, 2013 3 commits
-
-
Simon Horman authored
Convert code to use DEFINE_RES_MEM*() macros. These macros were already used in this file, this change makes their usage consistent throughout the file. Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Sergei Shtylyov authored
The correct model name is R-Car M1A or R8A77781; R8A77780 corresponds to R-Car M1S which is a SH based SoC. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> [horms+renesas@verge.net.au: manually applied] Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Laurent Pinchart authored
Both clock-r8a7740.c and clock-r8a7790.c define a div4_clks array as non-static. Compiling support for both SoCs thus result in a symbol redefinition. Fix it by defining the arrays as static. To avoid further similar issues, also define the main_clks as static. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
- 05 Jun, 2013 5 commits
-
-
Laurent Pinchart authored
Replace hardcoded pin numbers with the RCAR_GP_PIN macro to make the code match the documentation. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Laurent Pinchart authored
Initialize r8a7790 pinmuxing and register mappings for the two debug serial ports. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Kuninori Morimoto authored
SCIF0 support as 1st step Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Kuninori Morimoto authored
sh73a0 needs "sh_fsi2", not "sh_fsi2.0" Tested-by:
Hiep Cao Minh <cm-hiep@jinso.co.jp> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-
Magnus Damm authored
Use DEFINE_RES_MEM() and platform_device_register_simple() to save a couple of lines of code. Signed-off-by:
Magnus Damm <damm@opensource.se> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
-