- 05 Apr, 2012 14 commits
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Amir Vadai authored
This patch is using the DCB netlink to set rate limit per ETS TC Values are accepted in Kbps and rounded up to the nearest multiply of 100Mbps. Signed-off-by:
Amir Vadai <amirv@mellanox.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Amir Vadai authored
Although not specified in 8021Qaz spec, it could be useful to enable drivers whose HW supports setting a rate limit for an ETS TC. This patch adds this optional attribute to DCB netlink. To use it, drivers should implement and register the callbacks ieee_setmaxrate and ieee_getmaxrate. The units are 64 bits long and specified in Kbps to enable usage over both slow and very fast networks. Signed-off-by:
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Amir Vadai authored
Both tagged traffic and untagged traffic use tc tool mapping. Treat RDMA TOS same as IP TOS when mapping to SL Signed-off-by:
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Amir Vadai authored
Need to export this to enable drivers use rt_tos2priority() Signed-off-by:
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Amir Vadai authored
Since vlan egress map is only good for tagged traffic, need to have other mapping to be used by untagged traffic. For that, the driver uses sch_mqprio mapping. This mapping could be set by using tc tool from iproute2 package. Mapped UP will be used by the HW for QoS purposes, but won't go out on the wire. Signed-off-by:
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Amir Vadai authored
Set TSA, promised BW and PFC using IEEE 802.1qaz netlink commands. Signed-off-by:
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Amir Vadai authored
Adding QoS firmware commands: - mlx4_en_SET_PORT_PRIO2TC - set UP <=> TC - mlx4_en_SET_PORT_SCHEDULER - set promised BW, max BW and PG number Signed-off-by:
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Amir Vadai authored
Instead of relying on HW to change schedule queue by UP, schedule queue is fixed for a tx_ring, and UP in WQE is ignored in this aspect. This resolves two issues with untagged traffic: 1. untagged traffic has no UP in packet which is needed for QoS. The change above allows setting the schedule queue (and by that the UP) of such a stream. 2. BlueFlame uses the same field used by vlan tag. So forcing UP from QPC allows using BF for untagged but prioritized traffic. In old firmware that force UP is not supported, untagged traffic will not subject to QoS. Because UP is set by QP, need to always have a tx ring per UP, even if pfcrx module paramter is false. Signed-off-by:
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Yoshihiro Shimoda authored
The R8A7740 has a Gigabit Ethernet MAC. This patch supports it. Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
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Mike Sinkovsky authored
Based on original driver from chip manufacturer, but nearly full rewite. Tested and used in production with Blackfin BF531 embedded processor. Signed-off-by:
Mike Sinkovsky <msink@permonline.ru> Signed-off-by:
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Mike Sinkovsky authored
Based on original driver from chip manufacturer, but nearly full rewite. Tested and used in production with Blackfin BF531 embedded processor. Signed-off-by:
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Joe Perches authored
Convert the macro to inline function to check the arguments. Signed-off-by:
Joe Perches <joe@perches.com> Signed-off-by:
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Jiri Pirko authored
This patch introduces new team mode. It's TX port is selected by user-set BPF hash function. Signed-off-by:
Jiri Pirko <jpirko@redhat.com> Signed-off-by:
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Jiri Pirko authored
For transfering generic binary data (e.g. BPF code), introduce new binary option type. Signed-off-by:
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- 04 Apr, 2012 26 commits
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Giuseppe CAVALLARO authored
Signed-off-by:
Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by:
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Giuseppe CAVALLARO authored
If a specific clk_csr value is passed from the platform this means that the CSR Clock Range selection cannot be changed at run-time and it is fixed (as reported in the driver documentation). Viceversa the driver will try to set the MDC clock dynamically according to the actual clock input. Signed-off-by:
Deepak Sikri <deepak.sikri@st.com> Signed-off-by:
Francesco Virlinzi <francesco.virlinzi@st.com> Reviewed-by:
David Laight <david.laight@aculab.com> Signed-off-by:
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Giuseppe CAVALLARO authored
The CSR Clock Range has been reworked and new macros has been added in the platform header to allow the CSR Clock Range selection in the GMII Address Register. The previous work didn't add the other fields that can be used to achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. On such platforms, these are used indeed so this patch adds them. Signed-off-by:
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Giuseppe CAVALLARO authored
this patch adds the way to enable/disable the MAC clock when call the open/close and resume/restore functions. This has been tested on ST platforms and SPEAr; thanks to Francesco and Deepak. Signed-off-by:
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Deepak SIKRI authored
This patch removes the infinite waits from the mdio read and write interfaces. These infinite waits have been replaced by the timeout handling. In case if a time out occurs, an error is returned. Signed-off-by:
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Deepak SIKRI authored
This patch re-works the internal GMAC DMA parameters passed from the platform. In the past, we only passed the pbl but, with new core, other parameters can be passed and are mandatory on some platforms. New parameters are documented in stmmac.txt because this patch has an impact for many platforms. Signed-off-by:
Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by:
Vikas Manocha <vikas.manocha@st.com> Signed-off-by:
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Deepak SIKRI authored
The patch adds the macros to be used for MDC clock selection. The MDC clock frequency is based on scaled system clock, and has to be confined to a range of 1-2.5 MHz. Based on the input CSR clock, the scaling factor has to be selected. The platform specific code will provide the default value of this scaling factor, based on the input CSR clock. There is an option to set MDC clock higher than the IEEE 802.3 specified frequency limit of 2.5 MHz. This applies for the interfacing chips that support higher MDC clocks. The resultant higher clock of 12.5 MHz requires additional Macros to be defined for the clock divider corresponding to the to the following selection. ----------------------------------------- Selection MDC Clock ----------------------------------------- 1000 clk_csr_i/4 1001 clk_csr_i/6 1010 clk_csr_i/8 1011 clk_csr_i/10 1100 clk_csr_i/12 1101 clk_csr_i/14 1110 clk_csr_i/16 1111 clk_csr_i/18 This support has to be added both in the include file, as well as driver. The driver need to program the registers based on the interfacing chips. This would be more board specific information and needs to be passed through the platform code to the driver. This work would be carried out in the future patch set release. Signed-off-by:
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Deepak SIKRI authored
This patch sanities the RX coe and adds the Type-1 Rx checksum offload engine (COE). So the RX COE can be passed through the platform but can be fixed at run-time in case of the core has the HW capability register. Also to support the Type-1 Rx COE the driver must append the HW checksum at the end of payload in case the Rx checksum engine was used to offload the HW checksum. This v2 version also fixes the IPC that has to be enabled and verified. Signed-off-by:
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Deepak SIKRI authored
This patch explicitly defines the CSUM offload engine type which need (not mandatory) to be passed from the platform code. STMMAC core supports two check sum offload engine types- Type-1 & Type-2. Also, there are STMMAC cores that do not have the check sum offload capabilities. The behaviour of Type-1 & Type-2 cores related to provision of checksum increases the packet length for Type-1 cores by 2, as the checksum is appended at the end of data packet and the same is made accountable in the DMA status. The STMMAC cores beyond Version-3.5 provide HW interface registers which allows the user to read the HW capabilities, while to support the previous cores the information related to HW capabilities has to be provided from the platform code. The Type-1 cores which do not have the HW register interface need this information. This patch also updates the driver's doc. Signed-off-by:
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Srinivas Kandagatla authored
As stmmac mdio bus name prefix is hardcoded in the driver, this allows only phys on stmmac mdio buses to connect, however stmmac should allow phys on other mdio buses too. This patch adds new variable phy_bus_name to plat_stmmacenet_data struct to let the BSP decide which phy bus to be used by stmmac driver. A typical use-case is to have generic MDIO buses like mdio-gpio on top of stmmac. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@st.com> Acked-by:
Florian Fainelli <florian@openwrt.org> Signed-off-by:
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Jing Huang authored
Driver version update Signed-off-by:
Jing Huang <huangj@brocade.com> Signed-off-by:
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Jing Huang authored
Renamed following functions: bnad_cleanup_tx to bnad_destroy_tx bnad_free_all_txbufs to bnad_txq_cleanup bnad_free_txbufs to bnad_txcmpl_process bnad_tx to bnad_tx_complete bnad_cleanup_rx to bnad_destroy_rx bnad_reset_rcb to bnad_rcb_cleanup bnad_free_all_rxbufs to bnad_rxq_cleanup bnad_cq_cmpl_init to bnad_cq_cleanup bnad_alloc_n_post_rxbufs to bnad_rxq_post bnad_poll_cq to bnad_cq_process Signed-off-by:
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Jing Huang authored
The scheduling of tasklet and keeping the interrupts enabled makes interrupt reduntant. 20% of the Tx interrupts have nothing left to process or could not process as Tx tasklet was running. Signed-off-by:
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Jing Huang authored
This patch removes busy wait in tx/rx cleanup. bnad_cb_tx_cleanup() and bnad_cb_rx_cleanup() functions are called from irq context, and currently they do busy wait for the in-flight transmit or the currently executing napi polling routine to complete. To fix the issue, we create a workqueue to defer tx & rx cleanup processing, an in the tx rx cleanup handler, we will wait respective in flight processing to complete, before freeing the buffers. Signed-off-by:
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Jing Huang authored
Remove irrelevant code. Change to start Hearbeat failure moniter after IOC become operational. Signed-off-by:
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Jing Huang authored
Added NFC pause/resume logic. We only do NFC pause/resume if NFC version is greater than 0x143 and it was halted before, otherwise we revert to old NFC halt mechanism. Made changes to avoid clearing off the interrupts during the initial pll initialization. Signed-off-by:
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Jing Huang authored
Use init semaphore to serialize execution of the "unlock IOC semaphore" code. Added bfa_ioc_fwver_clear() function to clear the firmware header if last firmwar boot is not from driver. Signed-off-by:
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Rob Herring authored
The platform is removed, so there are no users of this driver. Signed-off-by:
Rob Herring <rob.herring@calxeda.com> Cc: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Cc: Jesse Brandeburg <jesse.brandeburg@intel.com> Cc: Bruce Allan <bruce.w.allan@intel.com> Cc: Carolyn Wyborny <carolyn.wyborny@intel.com> Cc: Don Skidmore <donald.c.skidmore@intel.com> Cc: Greg Rose <gregory.v.rose@intel.com> Cc: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Cc: Alex Duyck <alexander.h.duyck@intel.com> Cc: John Ronciak <john.ronciak@intel.com> Cc: netdev@vger.kernel.org Signed-off-by:
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Eric Dumazet authored
Probably a leftover from ancient code... Signed-off-by:
Eric Dumazet <eric.dumazet@gmail.com> Cc: Roland Stigge <stigge@antcom.de> Signed-off-by:
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Santosh Nayak authored
'break' is unnecessary after 'return' statement. Remove all such 'break' as clean up. Signed-off-by:
Santosh Nayak <santoshprasadnayak@gmail.com> Signed-off-by:
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Dmitry Kravkov authored
Commit b475d78f lacked two pairs of parenthesis, causing an overflow in the congestion management. Signed-off-by:
Dmitry Kravkov <dmitry@broadcom.com> Signed-off-by:
Yuval Mintz <yuvalmin@broadcom.com> Signed-off-by:
Eilon Greenstein <eilong@broadcom.com> Signed-off-by:
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Richard Cochran authored
Signed-off-by:
Richard Cochran <richardcochran@gmail.com> Signed-off-by:
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Richard Cochran authored
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Richard Cochran authored
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Richard Cochran authored
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Richard Cochran authored
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