1. 23 Jan, 2013 10 commits
    • Christoffer Dall's avatar
      KVM: ARM: User space API for getting/setting co-proc registers · 1138245c
      Christoffer Dall authored
      The following three ioctls are implemented:
       -  KVM_GET_REG_LIST
       -  KVM_GET_ONE_REG
       -  KVM_SET_ONE_REG
      
      Now we have a table for all the cp15 registers, we can drive a generic
      API.
      
      The register IDs carry the following encoding:
      
      ARM registers are mapped using the lower 32 bits.  The upper 16 of that
      is the register group type, or coprocessor number:
      
      ARM 32-bit CP15 registers have the following id bit patterns:
        0x4002 0000 000F <zero:1> <crn:4> <crm:4> <opc1:4> <opc2:3>
      
      ARM 64-bit CP15 registers have the following id bit patterns:
        0x4003 0000 000F <zero:1> <zero:4> <crm:4> <opc1:4> <zero:3>
      
      For futureproofing, we need to tell QEMU about the CP15 registers the
      host lets the guest access.
      
      It will need this information to restore a current guest on a future
      CPU or perhaps a future KVM which allow some of these to be changed.
      
      We use a separate table for these, as they're only for the userspace API.
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
      Signed-off-by: default avatarRusty Russell <rusty@rustcorp.com.au>
      Signed-off-by: default avatarChristoffer Dall <c.dall@virtualopensystems.com>
      1138245c
    • Christoffer Dall's avatar
      KVM: ARM: Emulation framework and CP15 emulation · 5b3e5e5b
      Christoffer Dall authored
      Adds a new important function in the main KVM/ARM code called
      handle_exit() which is called from kvm_arch_vcpu_ioctl_run() on returns
      from guest execution. This function examines the Hyp-Syndrome-Register
      (HSR), which contains information telling KVM what caused the exit from
      the guest.
      
      Some of the reasons for an exit are CP15 accesses, which are
      not allowed from the guest and this commit handles these exits by
      emulating the intended operation in software and skipping the guest
      instruction.
      
      Minor notes about the coproc register reset:
      1) We reserve a value of 0 as an invalid cp15 offset, to catch bugs in our
         table, at cost of 4 bytes per vcpu.
      
      2) Added comments on the table indicating how we handle each register, for
         simplicity of understanding.
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
      Signed-off-by: default avatarRusty Russell <rusty@rustcorp.com.au>
      Signed-off-by: default avatarChristoffer Dall <c.dall@virtualopensystems.com>
      5b3e5e5b
    • Christoffer Dall's avatar
      KVM: ARM: World-switch implementation · f7ed45be
      Christoffer Dall authored
      Provides complete world-switch implementation to switch to other guests
      running in non-secure modes. Includes Hyp exception handlers that
      capture necessary exception information and stores the information on
      the VCPU and KVM structures.
      
      The following Hyp-ABI is also documented in the code:
      
      Hyp-ABI: Calling HYP-mode functions from host (in SVC mode):
         Switching to Hyp mode is done through a simple HVC #0 instruction. The
         exception vector code will check that the HVC comes from VMID==0 and if
         so will push the necessary state (SPSR, lr_usr) on the Hyp stack.
         - r0 contains a pointer to a HYP function
         - r1, r2, and r3 contain arguments to the above function.
         - The HYP function will be called with its arguments in r0, r1 and r2.
         On HYP function return, we return directly to SVC.
      
      A call to a function executing in Hyp mode is performed like the following:
      
              <svc code>
              ldr     r0, =BSYM(my_hyp_fn)
              ldr     r1, =my_param
              hvc #0  ; Call my_hyp_fn(my_param) from HYP mode
              <svc code>
      
      Otherwise, the world-switch is pretty straight-forward. All state that
      can be modified by the guest is first backed up on the Hyp stack and the
      VCPU values is loaded onto the hardware. State, which is not loaded, but
      theoretically modifiable by the guest is protected through the
      virtualiation features to generate a trap and cause software emulation.
      Upon guest returns, all state is restored from hardware onto the VCPU
      struct and the original state is restored from the Hyp-stack onto the
      hardware.
      
      SMP support using the VMPIDR calculated on the basis of the host MPIDR
      and overriding the low bits with KVM vcpu_id contributed by Marc Zyngier.
      
      Reuse of VMIDs has been implemented by Antonios Motakis and adapated from
      a separate patch into the appropriate patches introducing the
      functionality. Note that the VMIDs are stored per VM as required by the ARM
      architecture reference manual.
      
      To support VFP/NEON we trap those instructions using the HPCTR. When
      we trap, we switch the FPU.  After a guest exit, the VFP state is
      returned to the host.  When disabling access to floating point
      instructions, we also mask FPEXC_EN in order to avoid the guest
      receiving Undefined instruction exceptions before we have a chance to
      switch back the floating point state.  We are reusing vfp_hard_struct,
      so we depend on VFPv3 being enabled in the host kernel, if not, we still
      trap cp10 and cp11 in order to inject an undefined instruction exception
      whenever the guest tries to use VFP/NEON. VFP/NEON developed by
      Antionios Motakis and Rusty Russell.
      
      Aborts that are permission faults, and not stage-1 page table walk, do
      not report the faulting address in the HPFAR.  We have to resolve the
      IPA, and store it just like the HPFAR register on the VCPU struct. If
      the IPA cannot be resolved, it means another CPU is playing with the
      page tables, and we simply restart the guest.  This quirk was fixed by
      Marc Zyngier.
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
      Signed-off-by: default avatarRusty Russell <rusty@rustcorp.com.au>
      Signed-off-by: default avatarAntonios Motakis <a.motakis@virtualopensystems.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarChristoffer Dall <c.dall@virtualopensystems.com>
      f7ed45be
    • Christoffer Dall's avatar
      KVM: ARM: Inject IRQs and FIQs from userspace · 86ce8535
      Christoffer Dall authored
      All interrupt injection is now based on the VM ioctl KVM_IRQ_LINE.  This
      works semantically well for the GIC as we in fact raise/lower a line on
      a machine component (the gic).  The IOCTL uses the follwing struct.
      
      struct kvm_irq_level {
      	union {
      		__u32 irq;     /* GSI */
      		__s32 status;  /* not used for KVM_IRQ_LEVEL */
      	};
      	__u32 level;           /* 0 or 1 */
      };
      
      ARM can signal an interrupt either at the CPU level, or at the in-kernel irqchip
      (GIC), and for in-kernel irqchip can tell the GIC to use PPIs designated for
      specific cpus.  The irq field is interpreted like this:
      
        bits:  | 31 ... 24 | 23  ... 16 | 15    ...    0 |
        field: | irq_type  | vcpu_index |   irq_number   |
      
      The irq_type field has the following values:
      - irq_type[0]: out-of-kernel GIC: irq_number 0 is IRQ, irq_number 1 is FIQ
      - irq_type[1]: in-kernel GIC: SPI, irq_number between 32 and 1019 (incl.)
                     (the vcpu_index field is ignored)
      - irq_type[2]: in-kernel GIC: PPI, irq_number between 16 and 31 (incl.)
      
      The irq_number thus corresponds to the irq ID in as in the GICv2 specs.
      
      This is documented in Documentation/kvm/api.txt.
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
      Signed-off-by: default avatarChristoffer Dall <c.dall@virtualopensystems.com>
      86ce8535
    • Christoffer Dall's avatar
      KVM: ARM: Memory virtualization setup · d5d8184d
      Christoffer Dall authored
      This commit introduces the framework for guest memory management
      through the use of 2nd stage translation. Each VM has a pointer
      to a level-1 table (the pgd field in struct kvm_arch) which is
      used for the 2nd stage translations. Entries are added when handling
      guest faults (later patch) and the table itself can be allocated and
      freed through the following functions implemented in
      arch/arm/kvm/arm_mmu.c:
       - kvm_alloc_stage2_pgd(struct kvm *kvm);
       - kvm_free_stage2_pgd(struct kvm *kvm);
      
      Each entry in TLBs and caches are tagged with a VMID identifier in
      addition to ASIDs. The VMIDs are assigned consecutively to VMs in the
      order that VMs are executed, and caches and tlbs are invalidated when
      the VMID space has been used to allow for more than 255 simultaenously
      running guests.
      
      The 2nd stage pgd is allocated in kvm_arch_init_vm(). The table is
      freed in kvm_arch_destroy_vm(). Both functions are called from the main
      KVM code.
      
      We pre-allocate page table memory to be able to synchronize using a
      spinlock and be called under rcu_read_lock from the MMU notifiers.  We
      steal the mmu_memory_cache implementation from x86 and adapt for our
      specific usage.
      
      We support MMU notifiers (thanks to Marc Zyngier) through
      kvm_unmap_hva and kvm_set_spte_hva.
      
      Finally, define kvm_phys_addr_ioremap() to map a device at a guest IPA,
      which is used by VGIC support to map the virtual CPU interface registers
      to the guest. This support is added by Marc Zyngier.
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarChristoffer Dall <c.dall@virtualopensystems.com>
      d5d8184d
    • Christoffer Dall's avatar
      KVM: ARM: Hypervisor initialization · 342cd0ab
      Christoffer Dall authored
      Sets up KVM code to handle all exceptions taken to Hyp mode.
      
      When the kernel is booted in Hyp mode, calling an hvc instruction with r0
      pointing to the new vectors, the HVBAR is changed to the the vector pointers.
      This allows subsystems (like KVM here) to execute code in Hyp-mode with the
      MMU disabled.
      
      We initialize other Hyp-mode registers and enables the MMU for Hyp-mode from
      the id-mapped hyp initialization code. Afterwards, the HVBAR is changed to
      point to KVM Hyp vectors used to catch guest faults and to switch to Hyp mode
      to perform a world-switch into a KVM guest.
      
      Also provides memory mapping code to map required code pages, data structures,
      and I/O regions  accessed in Hyp mode at the same virtual address as the host
      kernel virtual addresses, but which conforms to the architectural requirements
      for translations in Hyp mode. This interface is added in arch/arm/kvm/arm_mmu.c
      and comprises:
       - create_hyp_mappings(from, to);
       - create_hyp_io_mappings(from, to, phys_addr);
       - free_hyp_pmds();
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarChristoffer Dall <c.dall@virtualopensystems.com>
      342cd0ab
    • Christoffer Dall's avatar
      KVM: ARM: Initial skeleton to compile KVM support · 749cf76c
      Christoffer Dall authored
      Targets KVM support for Cortex A-15 processors.
      
      Contains all the framework components, make files, header files, some
      tracing functionality, and basic user space API.
      
      Only supported core is Cortex-A15 for now.
      
      Most functionality is in arch/arm/kvm/* or arch/arm/include/asm/kvm_*.h.
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
      Signed-off-by: default avatarRusty Russell <rusty@rustcorp.com.au>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarChristoffer Dall <c.dall@virtualopensystems.com>
      749cf76c
    • Christoffer Dall's avatar
      ARM: Section based HYP idmap · 9e9a367c
      Christoffer Dall authored
      Add a method (hyp_idmap_setup) to populate a hyp pgd with an
      identity mapping of the code contained in the .hyp.idmap.text
      section.
      
      Offer a method to drop this identity mapping through
      hyp_idmap_teardown.
      
      Make all the above depend on CONFIG_ARM_VIRT_EXT and CONFIG_ARM_LPAE.
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarChristoffer Dall <c.dall@virtualopensystems.com>
      9e9a367c
    • Christoffer Dall's avatar
      ARM: Add page table and page defines needed by KVM · cc577c26
      Christoffer Dall authored
      KVM uses the stage-2 page tables and the Hyp page table format,
      so we define the fields and page protection flags needed by KVM.
      
      The nomenclature is this:
       - page_hyp:        PL2 code/data mappings
       - page_hyp_device: PL2 device mappings (vgic access)
       - page_s2:         Stage-2 code/data page mappings
       - page_s2_device:  Stage-2 device mappings (vgic access)
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
      Christoffer Dall <c.dall@virtualopensystems.com>
      cc577c26
    • Will Deacon's avatar
      6abc749f
  2. 18 Jan, 2013 3 commits
    • Mark Rutland's avatar
      ARM: perf: simplify __hw_perf_event_init err handling · 9dcbf466
      Mark Rutland authored
      Currently __hw_perf_event_init has an err variable that's ignored right
      until the end, where it's initialised, conditionally set, and then used
      as a boolean flag deciding whether to return another error code.
      
      This patch removes the err variable and simplifies the associated error
      handling logic.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      9dcbf466
    • Mark Rutland's avatar
      ARM: perf: remove unnecessary checks for idx < 0 · 8f3b90b5
      Mark Rutland authored
      We currently check for hwx->idx < 0 in armpmu_read and armpmu_del
      unnecessarily. The only case where hwc->idx < 0 is when armpmu_add
      fails, in which case the event's state is set to
      PERF_EVENT_STATE_INACTIVE.
      
      The perf core will not attempt to read from an event in
      PERF_EVENT_STATE_INACTIVE, and so the check in armpmu_read is
      unnecessary. Similarly, if perf core cannot add an event it will not
      attempt to delete it, so the WARN_ON in armpmu_del is unnecessary.
      
      This patch removes these two redundant checks.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      8f3b90b5
    • Mark Rutland's avatar
      ARM: perf: handle armpmu_register failing · 76b8a0e4
      Mark Rutland authored
      Currently perf_pmu_register may fail for several reasons (e.g. being
      unable to allocate memory for the struct device it associates with each
      PMU), and while any error is propagated by armpmu_register, it is
      ignored by cpu_pmu_device_probe and not propagated to the caller.  This
      also results in a leak of a struct arm_pmu.
      
      This patch adds cleanup if armpmu_register fails, and updates the info
      messages to better differentiate this type of failure from a failure to
      probe the PMU type from the hardware or dt.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      76b8a0e4
  3. 16 Jan, 2013 1 commit
  4. 14 Jan, 2013 1 commit
  5. 11 Jan, 2013 2 commits
  6. 10 Jan, 2013 1 commit
  7. 09 Jan, 2013 6 commits
    • Linus Torvalds's avatar
      Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm · 5c49985c
      Linus Torvalds authored
      Pull ARM fixes from Russell King.
      
      * 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
        ARM: 7616/1: cache-l2x0: aurora: Use writel_relaxed instead of writel
        ARM: 7615/1: cache-l2x0: aurora: Invalidate during clean operation with WT enable
        ARM: 7614/1: mm: fix wrong branch from Cortex-A9 to PJ4b
        ARM: 7612/1: imx: Do not select some errata that depends on !ARCH_MULTIPLATFORM
        ARM: 7611/1: VIC: fix bug in VIC irqdomain code
        ARM: 7610/1: versatile: bump IRQ numbers
        ARM: 7609/1: disable errata work-arounds which access secure registers
        ARM: 7608/1: l2x0: Only set .set_debug on PL310 r3p0 and earlier
      5c49985c
    • Linus Torvalds's avatar
      Merge tag 'edac_fixes_for_3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp · 57a0c1e2
      Linus Torvalds authored
      Pull EDAC fixes from Borislav Petkov:
       "Two error path fixes causing a crash and a Kconfig fix for an issue
        which spilled all EDAC suboptions into the 'Device Drivers' menu."
      
      * tag 'edac_fixes_for_3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp:
        EDAC: Cleanup device deregistering path
        EDAC: Fix EDAC Kconfig menu
        EDAC: Fix kernel panic on module unloading
      57a0c1e2
    • Linus Torvalds's avatar
      mm: reinstante dropped pmd_trans_splitting() check · e53289c0
      Linus Torvalds authored
      The check for a pmd being in the process of being split was dropped by
      mistake by commit d10e63f2 ("mm: numa: Create basic numa page
      hinting infrastructure"). Put it back.
      Reported-by: default avatarDave Jones <davej@redhat.com>
      Debugged-by: default avatarHillf Danton <dhillf@gmail.com>
      Acked-by: default avatarAndrea Arcangeli <aarcange@redhat.com>
      Acked-by: default avatarMel Gorman <mgorman@suse.de>
      Cc: Kirill Shutemov <kirill@shutemov.name>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      e53289c0
    • Marc Dionne's avatar
      cred: Remove tgcred pointer from struct cred · 08c097fc
      Marc Dionne authored
      Commit 3a50597d ("KEYS: Make the session and process keyrings
      per-thread") removed the definition of the thread_group_cred structure,
      but left a now unused pointer in struct cred.
      Signed-off-by: default avatarMarc Dionne <marc.c.dionne@gmail.com>
      Signed-off-by: default avatarDavid Howells <dhowells@redhat.com>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      08c097fc
    • Linus Torvalds's avatar
      Merge tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc · 974b3358
      Linus Torvalds authored
      Pull ARM SoC fixes from Olof Johansson:
       "People are back from the holiday breaks, and it shows.  Here are a
        bunch of fixes for a number of platforms:
         - A couple of small fixes for Nomadik
         - A larger set of changes for kirkwood/mvebu
           - uart driver selection, dt clocks, gpio-poweroff fixups, a few
             __init annotation fixes and some error handling improvement in
             their xor dma driver.
         - i.MX had a couple of minor fixes (and a critical one for flexcan2
           clock setup)
         - MXS has a small board fix and a framebuffer bugfix
         - A set of fixes for Samsung Exynos, fixing default bootargs and some
           Exynos5440 clock issues
         - A set of OMAP changes including PM fixes and a few sparse warning
           fixups
      
        All in all a bit more positive code delta than we'd ideally want to
        see here, mostly from the OMAP PM changes, but nothing overly crazy."
      
      * tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (44 commits)
        ARM: clps711x: Fix bad merge of clockevents setup
        ARM: highbank: save and restore L2 cache and GIC on suspend
        ARM: highbank: add a power request clear
        ARM: highbank: fix secondary boot and hotplug
        ARM: highbank: fix typos with hignbank in power request functions
        ARM: dts: fix highbank cpu mpidr values
        ARM: dts: add device_type prop to cpu nodes on Calxeda platforms
        ARM: mx5: Fix MX53 flexcan2 clock
        ARM: OMAP2+: am33xx-hwmod: Fix wrongly terminated am33xx_usbss_mpu_irqs array
        pinctrl: mvebu: make pdma clock on dove mandatory
        ARM: Dove: Add pinctrl clock to DT
        dma: mv_xor: fix error handling for clocks
        dma: mv_xor: fix error handling of mv_xor_channel_add()
        arm: mvebu: Add missing ; for cpu node.
        arm: mvebu: Armada XP MV78230 has only three Ethernet interfaces
        arm: mvebu: Armada XP MV78230 has two cores, not one
        clk: mvebu: Remove inappropriate __init tagging
        ARM: Kirkwood: Use fixed-regulator instead of board gpio call
        ARM: Kirkwood: Fix missing sdio clock
        ARM: Kirkwood: Switch TWSI1 of 88f6282 to DT clock providers
        ...
      974b3358
    • Linus Torvalds's avatar
      Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux · ca5c8a4c
      Linus Torvalds authored
      Pull drm update from Dave Airlie:
       "Exynos and Radeon mostly, with a dma-buf and ttm fix thrown in.
      
        It's a bit big but its mostly exynos license fix ups and I'd rather
        not hold those up since its legally stuff.
      
        Radeon has a couple of fixes from dma engine work, TTM is just a
        locking fix, and dma-buf fix has been hanging around and I finally got
        a chance to review it."
      
      * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (30 commits)
        drm/ttm: fix fence locking in ttm_buffer_object_transfer
        drm/prime: drop reference on imported dma-buf come from gem
        drm/radeon: add quirk for d3 delay during switcheroo poweron for apple macbooks
        drm/exynos: move finish page flip to a common place
        drm/exynos: fimd: modify condition in fimd resume
        drm/radeon: fix DMA CS parser for r6xx linear copy packet
        drm/radeon: split r6xx and r7xx copy_dma functions
        drm/exynos: Use devm_clk_get in exynos_drm_gsc.c
        drm/exynos: Remove redundant NULL check in exynos_drm_gsc.c
        drm/exynos: Remove explicit freeing using devm_* APIs in exynos_drm_gsc.c
        drm/exynos: Use devm_clk_get in exynos_drm_rotator.c
        drm/exynos: Remove redundant NULL check in exynos_drm_rotator.c
        drm/exynos: Remove unnecessary devm_* freeing APIs in exynos_drm_rotator.c
        drm/exynos: Use devm_clk_get in exynos_drm_fimc.c
        drm/exynos: Remove redundant NULL check
        drm/exynos: Remove explicit freeing using devm_* APIs in exynos_drm_fimc.c
        drm/exynos: Use devm_kzalloc in exynos_drm_ipp.c
        drm/exynos: fix gem buffer allocation type checking
        drm/exynos: remove needless parenthesis.
        drm/exynos: fix incorrect interrupt induced by m2m operation.
        ...
      ca5c8a4c
  8. 08 Jan, 2013 16 commits