- 09 Feb, 2021 8 commits
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Kent Russell authored
Instead of caching the value during amdgpu_device_init, just call the function directly. This avoids issues where the unique_id hasn't been saved by the time that KFD's topology snapshot is done (e.g. Arcturus). KFD's topology information from the amdgpu_device was initially cached at KFD initialization due to amdkfd and amdgpu being separate modules. Now that they are combined together, we can directly call the functions that we need and avoid this unnecessary duplication and complexity. As a side-effect of this change, we also remove unique_id=0 for CPUs, which is obviously not unique. v2: Drop previous patch printing unique_id in hex Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Kenneth Feng authored
The power limit and clock ragne are different in AC mode and DC mode. Firmware does the setting after this feature is enabled. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Nirmoy Das authored
Enable gfx wave limiting for gfx jobs before pushing high priority compute jobs so that high priority compute jobs gets more resources to finish early. v2: use ring priority instead of job priority. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Nirmoy Das authored
Wave limiting can be use to load balance high priority compute jobs along with gfx jobs. When enabled, this will reserve ~75% of waves for compute jobs. We do not need this from gfx10 onwards because >=gfx10 has asynchronous compute tunneling to replace wave limit requirement. Signed-off-by:
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Nirmoy Das authored
For high priority compute to work properly we need to enable wave limiting on gfx pipe. Wave limiting is done through writing into mmSPI_WCL_PIPE_PERCENT_GFX register. Enable only one high priority compute queue to avoid race condition between multiple high priority compute queues writing that register simultaneously. Signed-off-by:
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Nirmoy Das authored
This patch consist of below related changes: 1 Rename ring->priority to ring->hw_prio. 2 Assign correct hardware ring priority. 3 Remove ring->priority_mutex as ring priority remains unchanged after initialization. 4 Remove unused ring->num_jobs. v3: remove ring->num_jobs. v2: remove ring->priority_mutex. Fixes: 33abcb1f ("drm/amdgpu: set compute queue priority at mqd_init") Signed-off-by:
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Bhawanpreet Lakha authored
[Why] The dm struct is only being used if DCN config is defined and this causes a unused variable warning if DCN option is not set. [How] Remove the compile flag so the variable is used (there also seems to be a duplicate guard due to a bad rebase) so remove the outer guard to fix the warning. Fixes this warning drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c: In function 'dm_set_vblank': drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:5380:33: warning: unused variable 'dm' [-Wunused-variable] Fixes: 98ab5f35 ("drm/amd/display: Fix deadlock during gpu reset v3") Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Alex Deucher authored
This reverts commit 4c3a3292. Bhawan's fix is better (less ifdefs), so revert this and apply Bhawan's. Signed-off-by:
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- 04 Feb, 2021 25 commits
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Arnd Bergmann authored
After all users of the 'dm' warnings got hidden in an #ifdef, the compiler started warning about it being unused: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5380:33: error: unused variable 'dm' [-Werror,-Wunused-variable] Add another such #ifdef. Fixes: 98ab5f35 ("drm/amd/display: Fix deadlock during gpu reset v3") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125124849.102037-1-arnd@kernel.org
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Dave Airlie authored
Merge tag 'amd-drm-next-5.12-2021-02-03' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.12-2021-02-03: amdgpu: - Display fixes and cleanups - Vangogh fixes - Fix possible race when there are timeouts on two rings - SR-IOV fixes - Add missing license - DCE 10/12 bpc fixes - Display MALL fixes - Fix SMU user preference settings persistence - Fix retry in gem allocate - Add new PCI DID - Fix for manual fan speed control on cards where it was problematic - Fix regression in pinning GTT - Misc display fixes - Misc code cleanups amdkfd: - Fix config handling - Fix regression in buffer free From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210204045717.3823-1-alexander.deucher@amd.comSigned-off-by:
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Dave Airlie authored
Merge tag 'mediatek-drm-next-5.12' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next Mediatek DRM Next for Linux 5.12 1. Decouple Mediatek DRM sub driver 2. Share mtk mutex driver for both DRM and MDP 3. Add support for SoC MT8183 Signed-off-by:
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Yongqiang Niu authored
Add matrix_bits and coeffs_precision to ccorr private data: - matrix bits of mt8183 is 10 - matrix bits of mt8192 is 11 Signed-off-by:
Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by:
Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by:
CK Hu <ck.hu@mediatek.com> Signed-off-by:
Chun-Kuang Hu <chunkuang.hu@kernel.org>
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Yongqiang Niu authored
Fix setting to follow hardware datasheet. The original error setting affects mt8192 display. Signed-off-by:
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Yongqiang Niu authored
ccorr ctm matrix bits will be different in mt8192. Signed-off-by:
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Yongqiang Niu authored
Enable dither function to improve the display quality. Signed-off-by:
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Yongqiang Niu authored
Enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch, ovl will hang up when more than 1 layer enabled. Signed-off-by:
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Yongqiang Niu authored
1. Add ovl private data 2. Add rdma private data 3. Add gamma privte data 4. Add main and external path module for crtc create Signed-off-by:
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Yongqiang Niu authored
Not all SoC has dither function in gamma module. Add private data to control this function setting. Signed-off-by:
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Yongqiang Niu authored
mt8183 gamma module will different with mt8173, so separate gamma for adding private data. Signed-off-by:
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Hsin-Yi Wang authored
Current implementation of mtk_dither_set() cast dev data to struct mtk_ddp_comp_dev. But other devices with different dev data would also call this function. Separate necessary parameters out so other device components (dither, gamma) can call this function. Signed-off-by:
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CK Hu authored
mtk mutex is used by DRM and MDP driver, and its function is SoC-specific, so move it to soc folder. Signed-off-by:
Matthias Brugger <matthias.bgg@gmail.com>
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CK Hu authored
Moving mutex resource management from client driver to mutex driver could prevent client drivers negotiating for resource management. Signed-off-by:
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CK Hu authored
mtk mutex is used by both drm and mdp driver, so change disp/ddp term to mutex to show that it's a common driver for drm and mdp. Signed-off-by:
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CK Hu authored
After mmsys routing function is moved out of mtk_drm_ddp.c, mtk_drm_ddp.c has only mtk mutex function, so rename it to match the function in it. Signed-off-by:
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CK Hu authored
Those file includings are useless, so remove them. Signed-off-by:
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Yongqiang Niu authored
Get the fifo size from device tree because each rdma in the same SoC may have different fifo size Signed-off-by:
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Yongqiang Niu authored
The orginal setting is not correct, fix it to follow hardware data sheet. If keep this error setting, mt8173/mt8183 display ok but mt8192 display abnormal. Fixes: 0664d139 ("drm/mediatek: Add AAL engine basic function") Signed-off-by:
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Yongqiang Niu authored
add description for postmask postmask is used control round corner for display frame Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Hsin-Yi Wang authored
Similar to commit a9d9fea7 ("drm/mediatek: mtk_dsi: Create connector for bridges"): Use the drm_bridge_connector helper to create a connector for pipelines that use drm_bridge. This allows splitting connector operations across multiple bridges when necessary, instead of having the last bridge in the chain creating the connector and handling all connector operations internally. Signed-off-by:
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Yongqiang Niu authored
rdma fifo size may be different even in same SOC, add this property to the corresponding rdma Signed-off-by:
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Yongqiang Niu authored
It's possible that state->base.fb is null. Add a check before access its format. Fixes: b6b1bb98 ("drm/mediatek: Turn off Alpha bit when plane format has no alpha") Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-intelDave Airlie authored
- WARN if plane src coords are too big (Ville) - Prevent double YUV range correction on HDR planes (Andres) - DP MST related Fixes (Sean, Imre) - More clean-up around DRAM detection code (Jose) - Actually async flips enable for all ilk+ platforms (Ville) Signed-off-by:
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ssh://git.freedesktop.org/git/tegra/linuxDave Airlie authored
drm/tegra: Changes for v5.12-rc1 Adds support for newer firmware image versions of the Video Image Composer (VIC) and adds a comment clarifying the use of the STREAMID registers. Fixes a couple of issues with display and gr2d on older Tegra SoCs such as Tegra114, as well as a runtime PM reference leak. Signed-off-by:
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- 02 Feb, 2021 7 commits
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Dan Carpenter authored
If the user passes a "level" value which is higher than 31 then that leads to shift wrapping. The undefined behavior will lead to a syzkaller stack dump. Fixes: 5632708f ("drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2)") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Bernard Zhao authored
Remove unneeded variable: "pattern". Signed-off-by:
Bernard Zhao <bernard@vivo.com> Signed-off-by:
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Jinzhou Su authored
Check GFX DPM and PG bit before enable GFXOFF on Vangogh smu post init. Signed-off-by:
Jinzhou Su <Jinzhou.Su@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - Better handling of dummy p-state table - Workaround for some legacy DP-VGA dongles - Add Freesync HDMI support to DMCU - Enable "trigger_hotplug" debugfs on all outputs - fix initial bounding box values for dcn3.02 - implement support for DID2.0 dsc passthrough - fix calculation for the pwl backlight curve - Fix multiple memory leaks Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Anson Jacob <Anson.Jacob@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Nikola Cornij authored
[why] Overlay won't move to a new positon if viewport size is smaller than what can be handled. It'd either disappear or stay at the old position. This condition is for example hit if overlay is moved too much outside of left or top edge of the screen, but it applies to any non-cursor plane type. [how] Reject this contidion at validation time. This gives the calling level a chance to handle this gracefully and avoid inconsistent behaivor. Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Joshua Aberback authored
[Why] Some scenarios where we use a UCLK frequency in between dummy p-state table entries result in a p-state hang, due to the table not having a close enough match, so the default DPM0 latency is used, which can be too long to support dummy p-state switching in these scenarios. [How] - old: match if current freq is within +- margin of table entry - new: find largest table entry that is lower than current freq + margin - lower than DPM0 will still use DPM0 Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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