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- 04 Mar, 2022 1 commit
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Peng Fan authored
i.MX93 CCM ROOT clock has a mux, gate and divider in one register, here is to combine all these into one composite clk and simplify clk tree. i.MX93 CCM is a new IP compared with i.MX8M, so introduce a new file. Reviewed-by:
Abel Vesa <abel.vesa@nxp.com> Reviewed-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220228020908.2810346-4-peng.fan@oss.nxp.comSigned-off-by:
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- 05 Nov, 2021 1 commit
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Alexander Stein authored
Only imx8m_clk_hw_composite_core needs to set this flag. Fixes: a60fe746 ("clk: imx: Rework all imx_clk_hw_composite wrappers") Signed-off-by:
Alexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/20211103123947.3222443-1-alexander.stein@ew.tq-group.comReviewed-by:
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- 30 Sep, 2021 8 commits
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Jacky Bai authored
On i.MX8ULP, the 'CLK_SET_RATE_PARENT' flag should NOT be set and according to the laest RM, the PFD divider value range seems will be changed in the future, so update the pfdv2 to include the specific support for i.MX8ULP. Signed-off-by:
Jacky Bai <ping.bai@nxp.com> Reviewed-by:
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Jacky Bai authored
On i.MX8ULP, some peripherals have a sw_rst control resides in the per device PCC clock control register, all others are same as i.MX7ULP, so update the 7ulp clock composite driver to support i.MX8ULP to maxmimize the code reuse. Signed-off-by:
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Jacky Bai authored
The PLLs used on i.MX8ULP is mostly the same as on i.MX7ULP, except the PLL register offset is changed. Change the PLLv4 driver for code reuse on i.MX7ULP and i.MX8ULP. Signed-off-by:
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Abel Vesa authored
It looks much cleaner to just have a macro compared to having a function that passes NULL as dev to the lower-level imx_dev_clk_hw_pll14xx. Signed-off-by:
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Abel Vesa authored
Rather than having multiple different macros for each different type of imx8m_clk_hw_composite, implement them in such a way so we can take advantage the most of the already defined simpler types. Basically, we end up having one low-level __imx8m_clk_hw_composite function, a wrapper to simplify the parents related arguments called _imx8m_clk_hw_composite and then all the types can use those for each specific case. Signed-off-by:
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Abel Vesa authored
Instead of having multiple inline functions that were calling clk_hw_register_divider, implement a generic low-level __imx_clk_hw_divider and implement the rest as macros that pass on as arguments whatever is needed in each case. Signed-off-by:
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Abel Vesa authored
Instead of having multiple inline functions that were calling clk_hw_register_mux, implement a generic low-level __imx_clk_hw_mux and implement the rest as macros that pass on as arguments whatever is needed in each case. Signed-off-by:
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Abel Vesa authored
Instead of having multiple inline functions that were calling clk_hw_register_gate2, implement a generic low-level __imx_clk_hw_gate2 and implement the rest as macros that pass on as arguments whatever is needed in each case. Signed-off-by:
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- 17 Sep, 2021 3 commits
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Abel Vesa authored
Instead of having multiple inline functions that were calling clk_hw_register_gate, implement a generic low-level __imx_clk_hw_gate and implement the rest as macros that pass on as arguments whatever is needed in each case. Signed-off-by:
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Abel Vesa authored
Implement the clk based helpers as macros rather than as inline functions. Once all the provider drivers have switch to clk_hw, all the clk based macros will go away. Signed-off-by:
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Abel Vesa authored
Remove all the helpers that are not referenced anywhere anymore. Most of them are not clk_hw based. The rest are passing the device as an argument and were intented for BLK_CTL driver usage, but that is not the case anymore since the BLK_CTL is (or will be) implemented outside of CCF. - imx_clk_divider2 - imx_clk_gate2_shared2 - imx_clk_gate3 - imx_clk_gate4 - imx_clk_frac_pll - imx_clk_sscg_pll - imx_clk_pll14xx - imx_clk_pll14xx - imx_clk_divider2_flags - imx_dev_clk_hw_gate - imx_dev_clk_hw_gate_shared - imx_clk_gate3_flags - imx_clk_gate4_flags - imx_dev_clk_hw_mux - imx_clk_mux2 - imx_dev_clk_hw_mux_flags - imx8m_clk_composite_flags - __imx8m_clk_composite - imx8m_clk_composite - imx8m_clk_composite_critical Signed-off-by:
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- 24 Aug, 2021 1 commit
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Ahmad Fatoum authored
On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service for DDR frequency scaling. The imx8m-ddrc-devfreq driver calls the SiP and then does clk_set_parent on the DDR muxes to synchronize the clock tree. Since 936c3836 ("clk: imx: fix composite peripheral flags"), these TF-A managed muxes have SET_PARENT_GATE set, which results in imx8m-ddrc-devfreq's clk_set_parent after SiP failing with -EBUSY: echo 25000000 > userspace/set_freq imx8m-ddrc-devfreq 3d400000.memory-controller: failed to set dram_apb parent: -16 Fix this by adding a new i.MX composite flag for firmware managed clocks, which clears SET_PARENT_GATE. This is safe to do, because updating the Linux clock tree to reflect reality will always be glitch-free. Fixes: 936c3836 ("clk: imx: fix composite peripheral flags") Signed-off-by:
Ahmad Fatoum <a.fatoum@pengutronix.de> Reviewed-by:
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- 04 Apr, 2021 1 commit
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Adam Ford authored
Most if not all i.MX SoC's call a function which enables all UARTS. This is a problem for users who need to re-parent the clock source, because any attempt to change the parent results in an busy error due to the fact that the clocks have been enabled already. clk: failed to reparent uart1 to sys_pll1_80m: -16 Instead of pre-initializing all UARTS, scan the device tree to see which UART clocks are associated to stdout, and only enable those UART clocks if it's needed early. This will move initialization of the remaining clocks until after the parenting of the clocks. When the clocks are shutdown, this mechanism will also disable any clocks that were pre-initialized. Fixes: 9461f7b3 ("clk: fix CLK_SET_RATE_GATE with clock rate protection") Suggested-by:
Aisheng Dong <aisheng.dong@nxp.com> Signed-off-by:
Adam Ford <aford173@gmail.com> Reviewed-by:
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- 05 Nov, 2020 1 commit
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Peng Fan authored
noc/axi/ahb are bus clk, not peripheral clk. Since peripheral clk has a limitation that for peripheral clock slice, IP clock slices must be stopped to change the clock source. However if the bus clk is marked as critical clk peripheral, the assigned clock parent operation will fail. So we added CLK_SET_PARENT_GATE flag to avoid glitch. And add imx8m_clk_hw_composite_bus_critical for bus critical clock usage Fixes: 936c3836 ("clk: imx: fix composite peripheral flags") Reviewed-by:
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- 02 Nov, 2020 2 commits
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Abel Vesa authored
On some i.MX8 platforms, there are HW gates that share the same bit. So in order to make this clock type more usable, use a mask to specify how many bits belong to those HW gates. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Abel Vesa authored
This was a hack which would allow multiple HW gates to be controlled by a single bit. The only user of this is the imx_dev_clk_hw_gate_shared which is not used anywhere as of now. Basically, complicates the logic of the driver for no reason. Signed-off-by:
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- 22 Aug, 2020 2 commits
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Anson Huang authored
It is better to explicitly include the required header file rather then get it through some recursive include. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Acked-by:
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Anson Huang authored
There are more and more requirements of building SoC specific drivers as modules, add support for building i.MX common clock driver as module to meet the requirement. Signed-off-by:
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- 21 May, 2020 1 commit
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Peng Fan authored
Introduce imx8m_clk_hw_composite_bus api for bus clk root slice usage. Because the mux switch sequence issue, we could not reuse Peripheral Clock Slice code, need use composite specific mux operation. Signed-off-by:
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- 29 Apr, 2020 3 commits
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Abel Vesa authored
All the imx clocks that need to be registered by the audiomix need to pass on the device so that the runtime PM support could work properly. Signed-off-by:
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Abel Vesa authored
In order to allow runtime PM, the device needs to be passed on to the register function. Audiomix clock controller, used on i.MX8MP and future platforms, registers a pll14xx and has runtime PM support. Signed-off-by:
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Abel Vesa authored
Audiomix on i.MX8MP registers two gates that share the same enable count but use the same bit to control the gate instead of two bits. By adding the flag IMX_CLK_GATE2_SINGLE_BIT we allow the gate2 to use the generic gate ops for enable, disable and is_enabled. For the disable_unused, nothing happens if this flag is specified. Signed-off-by:
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- 14 Feb, 2020 1 commit
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Peng Fan authored
There are several clock slices, current composite code only support bus/ip clock slices, it could not support core slice. So introduce a new API imx8m_clk_hw_composite_core to support core slice. To core slice, post divider with 3 bits width and no pre divider. Other fields are same as bus/ip slices. Add a flag IMX_COMPOSITE_CORE for the usecase. Reviewed-by:
Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by:
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- 12 Jan, 2020 1 commit
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Anson Huang authored
Switch the imx_clk_gate4_flags() function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by:
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- 23 Dec, 2019 5 commits
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Peng Fan authored
Switch the imx_clk_hw_gate3_flags function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Reviewed-by:
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Peng Fan authored
Introduce hw based API imx_clk_hw_mux2_flags, then we could convert i.MX8MN clk driver to use hw based APIs. Signed-off-by:
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Peng Fan authored
There is a non hw API based imx_unregister_clocks to unregister clocks when of_clk_add_provider failed. Add a hw API based imx_unregister_hw_clocks when of_clk_add_hw_provider failed. Reviewed-by:
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Peng Fan authored
Switch the imx8m_clk_hw_composite_flags function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Reviewed-by:
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Peng Fan authored
Switch the imx_clk_pll14xx function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Reviewed-by:
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- 11 Dec, 2019 9 commits
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Abel Vesa authored
Renaming the imx_clk_divider_gate register function to imx_clk_hw_divider_gate to be more obvious it is clk_hw based. Signed-off-by:
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Abel Vesa authored
Renaming the imx_clk_pfdv2 register function to imx_clk_hw_pfdv2 to be more obvious it is clk_hw based. Signed-off-by:
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Abel Vesa authored
Renaming the imx_clk_pllv4 register function to imx_clk_hw_pllv4 to be more obvious it is clk_hw based. Signed-off-by:
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Abel Vesa authored
Renaming the imx_clk_frac_pll and imx_clk_sccg_pll register functions to imx_clk_hw_frac_pll, respectively imx_clk_hw_sccg_pll to be more obvious that they are clk_hw based. Signed-off-by:
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Abel Vesa authored
Renaming the imx7ulp_clk_composite register function to imx7ulp_clk_hw_composite to show it is clk_hw based. Signed-off-by:
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Abel Vesa authored
Switch the imx_clk_pllv2 register function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by:
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Abel Vesa authored
Switch the imx_clk_pllv1 register function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by:
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Abel Vesa authored
Replacing with macros all the clk based API helpers we reduce the code duplication. The end goal is to get rid of all these macros when there will be no more users of the clk based API, that is, when all the i.MX clock provider drivers will be switched completely to the clk_hw based API. This is another step in moving away from the non clk_hw based API usage throughout the i.MX clock drivers. The reason for doing that is to have a clear split between the clock provider and the clock consumer API. Signed-off-by:
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Abel Vesa authored
According to the manual the acronym stands for Spread Sprectum Clock Generator. Signed-off-by:
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