1. 03 Feb, 2012 3 commits
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  11. 22 Jan, 2012 1 commit
  12. 20 Jan, 2012 2 commits
    • Fabio Estevam's avatar
      ASoC: mxs: Fix mxs-saif timeout · 6b35f924
      Fabio Estevam authored
      On a mx28evk board the following errors happens on mxs-sgtl5000 probe:
      
      [    0.660000] saif0_clk_set_rate: divider writing timeout
      [    0.670000] mxs-sgtl5000: probe of mxs-sgtl5000.0 failed with error -110
      [    0.670000] ALSA device list:
      [    0.680000]   No soundcards found.
      
      This timeout happens because clk_set_rate will result in writing to the DIV bits
      of register HW_CLKCTRL_SAIF0 with the saif clock gated (CLKGATE bit set to one).
      
      MX28 Reference states the following about CLKGATE:
      
      "The DIV field can change ONLY when this clock gate bit field is low."
      
      So call clk_prepare_enable prior to clk_set_rate to fix this problem.
      
      After this change the mxs-saif driver can be correctly probed and audio is functional.
      Signed-off-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
      Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
      6b35f924
    • Mark Brown's avatar
      ASoC: Disable register synchronisation for low frequency WM8996 SYSCLK · fed22007
      Mark Brown authored
      With a low frequency SYSCLK and a fast I2C clock register synchronisation
      may occasionally take too long to take effect, causing I/O issues. Disable
      synchronisation in order to avoid any issues.
      Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
      Cc: stable@kernel.org
      fed22007