- 06 Jun, 2024 24 commits
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Stephen Boyd authored
It's simpler to reason about things if we disable nodes instead of deleting them. Disable the second usb type-c connector node on quackingstick instead of deleting it so that we can reason about ports more easily. Cc: cros-qcom-dts-watchers@chromium.org Cc: Bjorn Andersson <andersson@kernel.org> Cc: Konrad Dybcio <konrad.dybcio@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Conor Dooley <conor+dt@kernel.org> Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: Pin-yen Lin <treapking@chromium.org> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20240604214233.3551692-2-swboyd@chromium.orgSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Krzysztof Kozlowski authored
Interrupt flags 0x2008 looks like some downstream copy-paste, because generic GPIOLIB code, used by Qualcomm pin controller drivers, ignores flags outside of IRQ_TYPE_SENSE_MASK. Probably the intention was to pass just 0x8, so IRQ_TYPE_LEVEL_LOW. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # SM8450 PDX223 Link: https://lore.kernel.org/r/20240605160032.150587-4-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Krzysztof Kozlowski authored
Interrupt flags 0x2008 looks like some downstream copy-paste, because generic GPIOLIB code, used by Qualcomm pin controller drivers, ignores flags outside of IRQ_TYPE_SENSE_MASK. Probably the intention was to pass just 0x8, so IRQ_TYPE_LEVEL_LOW. Signed-off-by:
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Krzysztof Kozlowski authored
Interrupt flags 0x2008 looks like some downstream copy-paste, because generic GPIOLIB code, used by Qualcomm pin controller drivers, ignores flags outside of IRQ_TYPE_SENSE_MASK. Probably the intention was to pass just 0x8, so IRQ_TYPE_LEVEL_LOW. Signed-off-by:
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Krzysztof Kozlowski authored
Interrupt flags 0x2008 looks like some downstream copy-paste, because generic GPIOLIB code, used by Qualcomm pin controller drivers, ignores flags outside of IRQ_TYPE_SENSE_MASK. Probably the intention was to pass just 0x8, so IRQ_TYPE_LEVEL_LOW. Signed-off-by:
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Abel Vesa authored
Add the pmic-glink node and describe all 3 USB Type-C connectors. Do this for USB only, for now. The DP ports will come at a later stage since they use muxes. Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Reviewed-by:
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Abel Vesa authored
Add the pmic-glink node and describe all 3 USB Type-C connectors. Do this for USB only, for now. The DP ports will come at a later stage since they use retimers. Signed-off-by:
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Abel Vesa authored
Describe the port/endpoints graph between the USB/DP combo PHYs and their corresponding DP controllers. Signed-off-by:
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Bjorn Andersson authored
Merge the arm64-fixes-for-6.10 branch into arm64-for-6.11 to resolve the merge conflict caused by pmic-glink and reserved-memory introduction at the same place in the x1e80100 crd and qcp dts files.
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Neil Armstrong authored
With the SM8650-HDK, a Display Card kit can be connected to provide a VTDR6130 display with Goodix Berlin Touch controller. In order to route the DSI lanes to the connector for the Display Card kit, a switch must be changed on the board. The HDMI nodes are disabled since the DSI lanes are shared with the DSI to HDMI transceiver. Add support for this card as an overlay and apply it it at build-time to the sm8650-hdk dtb. Reviewed-by:
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Tested-by:
Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240606-topic-sm8650-upstream-hdk-v6-1-fb034fe864cc@linaro.orgSigned-off-by:
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Aboothahir U authored
Add charger to PM660 PMIC. Readings from round-robin ADC are needed for charger to function, so add it as well. Signed-off-by:
Aboothahir U <aboothahirpkd@gmail.com> Signed-off-by:
Barnabás Czémán <trabarni@gmail.com> Link: https://lore.kernel.org/r/20240606-pm660-charger-rrdac-v1-1-a95d4da24f3b@gmail.comSigned-off-by:
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Abel Vesa authored
The actual size of the DBI region is 0xf20 and the start of the ELBI region is 0xf40, according to the documentation. So fix them. While at it, add the MHI region as well. Fixes: 5eb83fc1 ("arm64: dts: qcom: x1e80100: Add PCIe nodes") Reviewed-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240604-x1e80100-dts-fixes-pcie6a-v2-1-0b4d8c6256e5@linaro.orgSigned-off-by:
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Raymond Hackley authored
The phones listed below have Richtek RT5033 PMIC and charger. Add them to the device trees. - Samsung Galaxy Core Prime LTE - Samsung Galaxy Grand Prime Cc: Jakob Hauser <jahau@rocketmail.com> Signed-off-by:
Raymond Hackley <raymondhackley@protonmail.com> Link: https://lore.kernel.org/r/20240601115321.25314-4-raymondhackley@protonmail.comSigned-off-by:
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Raymond Hackley authored
Some variants of Samsung Galaxy Core Prime LTE / Grand Prime LTE have a Samsung S3FWRN5 NFC chip that works quite well with the s3fwrn5 driver in the Linux NFC subsystem. The clock setup for the NFC chip is a bit special (although this seems to be a common approach used for Qualcomm devices with NFC): The NFC chip has an output GPIO that is asserted whenever the clock is needed to function properly. On the A3/A5 this is wired up to PM8916 GPIO2, which is then configured with a special function (NFC_CLK_REQ or BB_CLK2_REQ). Enabling the rpmcc RPM_SMD_BB_CLK2_PIN clock will then instruct PM8916 to automatically enable the clock whenever the NFC chip requests it. The advantage is that the clock is only enabled when needed and we don't need to manage it ourselves from the NFC driver. Signed-off-by:
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Joe Mason authored
The Samsung Galaxy Grand Prime CAN has a Samsung S3FWRN5 NFC chip that works quite well with the s3fwrn5 driver in the Linux NFC subsystem. The clock setup for the NFC chip is a bit special (although this seems to be a common approach used for Qualcomm devices with NFC): The NFC chip has an output GPIO that is asserted whenever the clock is needed to function properly. On the A3/A5 this is wired up to PM8916 GPIO2, which is then configured with a special function (NFC_CLK_REQ or BB_CLK2_REQ). Enabling the rpmcc RPM_SMD_BB_CLK2_PIN clock will then instruct PM8916 to automatically enable the clock whenever the NFC chip requests it. The advantage is that the clock is only enabled when needed and we don't need to manage it ourselves from the NFC driver. Signed-off-by:
Joe Mason <buddyjojo06@outlook.com> [Stephan: Put NFC pinctrl into common dtsi to share it with other variants] Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> [Raymond: Use interrupts-extended. Keep &blsp_i2c6 enabled by default] Signed-off-by:
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Alexandre Messier authored
Add a compatible for the HTC One (M8), which is based on the MSM8974Pro SoC. Signed-off-by:
Alexandre Messier <alex@me.ssier.org> Acked-by:
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Abel Vesa authored
The CRD board doesn't have the 4th SMB2360 PMIC populated while the QCP does. So enable it on QCP only. This fixes the warning for the missing PMIC on CRD as well. Fixes: 2559e61e ("arm64: dts: qcom: x1e80100-pmics: Add the missing PMICs") Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Tested-by:
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Krishna Kurapati authored
On SC7280, in host mode, it is observed that stressing out controller results in HC died error: xhci-hcd.12.auto: xHCI host not responding to stop endpoint command xhci-hcd.12.auto: xHCI host controller not responding, assume dead xhci-hcd.12.auto: HC died; cleaning up And at this instant only restarting the host mode fixes it. Disable SuperSpeed instances in park mode for SC7280 to mitigate this issue. Reported-by:
Doug Anderson <dianders@google.com> Cc: stable@vger.kernel.org Fixes: bb9efa59 ("arm64: dts: qcom: sc7280: Add USB related nodes") Signed-off-by:
Krishna Kurapati <quic_kriskura@quicinc.com> Reviewed-by:
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Krishna Kurapati authored
On SC7180, in host mode, it is observed that stressing out controller results in HC died error: xhci-hcd.12.auto: xHCI host not responding to stop endpoint command xhci-hcd.12.auto: xHCI host controller not responding, assume dead xhci-hcd.12.auto: HC died; cleaning up And at this instant only restarting the host mode fixes it. Disable SuperSpeed instances in park mode for SC7180 to mitigate this issue. Reported-by:
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Dmitry Baryshkov authored
The L9A regulator is used to further control voltage regulators on the board. It can be used to disable VBAT_mains, 1.8V, 3.3V, 5V rails). Make sure that is stays always on to prevent undervolting of these volage rails. Fixes: 8d58a8c0 ("arm64: dts: qcom: Add base qrb4210-rb2 board dts") Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
On the Qualcomm RB2 platform the I2C bus connected to the LT9611UXC bridge under some circumstances can go into a state when all transfers timeout. This causes both issues with fetching of EDID and with updating of the bridge's firmware. While we are debugging the issue, switch corresponding I2C bus to use i2c-gpio driver. While using i2c-gpio no communication issues are observed. This patch is asusmed to be a temporary fix, so it is implemented in a non-intrusive manner to simply reverting it later. Fixes: f7b01e07 ("arm64: dts: qcom: qrb4210-rb2: Enable display out") Cc: stable@vger.kernel.org Signed-off-by:
Caleb Connolly <caleb.connolly@linaro.org> Link: https://lore.kernel.org/r/20240605-rb12-i2c2g-pio-v2-2-946f5d6b6948@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
On the Qualcomm RB1 platform the I2C bus connected to the LT9611UXC bridge under some circumstances can go into a state when all transfers timeout. This causes both issues with fetching of EDID and with updating of the bridge's firmware. While we are debugging the issue, switch corresponding I2C bus to use i2c-gpio driver. While using i2c-gpio no communication issues are observed. This patch is asusmed to be a temporary fix, so it is implemented in a non-intrusive manner to simply reverting it later. Fixes: 616eda24 ("arm64: dts: qcom: qrb2210-rb1: Set up HDMI") Cc: stable@vger.kernel.org Signed-off-by:
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Neil Armstrong authored
When triggering I2S SE DMA transfers on the 6th Serial Element, we get some timeouts and finally a fatal SMMU crash because the I2C6 lines are shared with the secure firmware in order to handle the SMB1396 charger from the secure side. In order to make thing work flawlessly we need to allow more SIDs while running our SE DMA transfers, thus add the 0x3 mark to allow the 0xa0 SID to trigger while we trigger an 0xa3 SID from Linux. This crash doesn't happen on the QRD platform since the SE6 is configured differently, with FIFO mode disabled, thus GPI DMA is used and we cannot exercise SE DMA on this interface. The crash only happens when large tranfers occurs (>32 bytes) since the driver is designed to use the SE DMA in this case, and there's no way to mark the SE DMA as disabled or mark the GPI DMA as preferred since the FIFO/SE DMA will be used is FIFO is not disabled. Signed-off-by:
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Krzysztof Kozlowski authored
Replace hard-coded interrupt parts (GIC, flags) with standard defines for readability. No changes in resulting DTBs. Signed-off-by:
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- 04 Jun, 2024 6 commits
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Luca Weiss authored
Instead of passing the syscon to the various nodes, use the mbox interface using the mboxes property. Signed-off-by:
Luca Weiss <luca@z3ntu.xyz> Reviewed-by:
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Luca Weiss authored
Instead of passing the syscon to the various nodes, use the mbox interface using the mboxes property. Signed-off-by:
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Luca Weiss authored
Instead of passing the syscon to the various nodes, use the mbox interface using the mboxes property. Signed-off-by:
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Luca Weiss authored
Instead of passing the syscon to the various nodes, use the mbox interface using the mboxes property. Signed-off-by:
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Luca Weiss authored
Instead of passing the syscon to the various nodes, use the mbox interface using the mboxes property. Signed-off-by:
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Cong Zhang authored
The INTID of EL2 non-secure physical timer is 26. In linux, the IRQ number has a fixed 16 offset for PPIs. Therefore, the linux IRQ number of EL2 non-secure physical timer should be 10 (26 - 16). Fixes: 603f96d4 ("arm64: dts: qcom: add initial support for qcom sa8775p-ride") Signed-off-by:
Cong Zhang <quic_congzhan@quicinc.com> Reviewed-by:
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- 01 Jun, 2024 10 commits
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Dmitry Baryshkov authored
Device nodes should have generic names. Use 'clock-controller@' as a GCC node name instead of a non-generic 'gcc@'. Signed-off-by:
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Dmitry Baryshkov authored
Device nodes should have generic names. Use 'clock-controller@' as a GCC node name instead of a non-generic 'gcc@'. Signed-off-by:
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Dmitry Baryshkov authored
On IPQ9574 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by:
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Dmitry Baryshkov authored
On IPQ5332 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by:
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Dmitry Baryshkov authored
On IPQ5018 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by:
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Dmitry Baryshkov authored
The commit 65931e59 ("arm64: dts: qcom: sm8650: move USB graph to the SoC dtsi") and commit fbb22a18 ("arm64: dts: qcom: sm8650: move PHY's orientation-switch to SoC dtsi") have moved some of the properties from the board DT files to the sm8650.dtsi. As the patch for sm8650 HDK predates those commits, it still had those properties inside. Drop these duplicate proerties from the sm8650-hdk.dts. Signed-off-by:
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Luca Weiss authored
Configure the Type-C and VBUS regulator on PM7250B and wire it up to the USB PHY, so that USB role and orientation switching works. For now USB Power Delivery properties are skipped / disabled, so that the (presumably) bootloader-configured charger doesn't get messed with and we can charge the phone with at least some amount of power. Reviewed-by:
Luca Weiss <luca.weiss@fairphone.com> Reviewed-by:
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Luca Weiss authored
Type-C port management functionality lives inside of the PMIC block on pm7250b. The Type-C port management logic controls orientation detection, vbus/vconn sense and to send/receive Type-C Power Domain messages. Reviewed-by:
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Luca Weiss authored
Add the required DTS node for the USB VBUS output regulator, which is available on PM7250B. This will provide the VBUS source to connected peripherals. Reviewed-by:
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Abel Vesa authored
On both the CRD and QCP, on PCIe 6a sits the NVMe. Add the 3.3V gpio-controlled regulator and the clkreq, perst and wake gpios as resources for the PCIe 6a. Signed-off-by:
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