Commits · 14abd038a7a209193c58ee7dde01ef4bf1523a91 · Kirill Smelkov / linux

07 Jul, 2011 40 commits

ARM: perf: add support for the Cortex-A15 PMU · 14abd038

Will Deacon authored Jan 19, 2011

This patch adds support for the Cortex-A15 PMU to the ARMv7
perf-event backend.
Signed-off-by: Will Deacon <will.deacon@arm.com>

14abd038

ARM: perf: add support for the Cortex-A5 PMU · 0c205cbe

Will Deacon authored Jun 03, 2011

This patch adds support for the Cortex-A5 PMU to the ARMv7 perf-event
backend.
Signed-off-by: Will Deacon <will.deacon@arm.com>

0c205cbe

ARM: perf: add PMUv2 common event definitions · 6d4eaf99

Will Deacon authored Jan 19, 2011

The PMUv2 specification reserves a number of event encodings
for common events.

This patch adds these events to the common event enumeration
in preparation for PMUv2 cores, such as Cortex-A15.
Acked-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

6d4eaf99

ARM: perf: remove confusing comment from v7 perf events backend · 7b35fa47

Will Deacon authored Jun 03, 2011

The comment about measuring TLB misses and refills in the ARMv7 perf
backend makes little sense and refers loosely to raw counters that
should be used instead.

This patch removes the comments to avoid any confusion.
Signed-off-by: Will Deacon <will.deacon@arm.com>

7b35fa47

ARM: proc: add proc info for Cortex-A15MP using classic page tables · 7665d9d2

Will Deacon authored Jan 12, 2011

Multicore implementations of the Cortex-A15 require bit 6 of the
auxiliary control register to be set in order for cache and TLB
maintenance operations to be broadcast between CPUs.

This patch adds a new proc_info structure for Cortex-A15, which enables
the SMP bit during setup and includes the new HWCAP for integer
division.
Signed-off-by: Will Deacon <will.deacon@arm.com>

7665d9d2

ARM: proc: add Cortex-A5 proc info · 15eb169b

Pawel Moll authored May 20, 2011

This patch adds processor info for ARM Ltd. Cortex A5,
which has SCU initialisation procedure identical to A9.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

15eb169b

ARM: proc: convert v7 proc infos into a common macro · dc939cd8

Pawel Moll authored May 20, 2011

As most of the proc info content is common across all v7
processors, this patch converts existing A9 and generic v7
descriptions into a macro (allowing extra flags in future).
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

dc939cd8

ARM: vfp: add VFPv4 capability detection and populate elf_hwcap · 18b9dc13

Will Deacon authored Jun 08, 2011

The presence of VFPv4 cannot be detected simply by looking at the FPSID
subarchitecture field, as a value >= 2 signifies the architecture as
VFPv3 or later.

This patch reads from MVFR1 to check whether or not the fused multiply
accumulate instructions are supported. Since these are introduced with
VFPv4, this tells us what we need to know.
Signed-off-by: Will Deacon <will.deacon@arm.com>

18b9dc13

ARM: hwcaps: add new HWCAP defines for ARMv7-A · 254cdf8e

Will Deacon authored Jun 03, 2011

Modern ARMv7-A cores can optionally implement these new hardware
features:

- VFPv4:
    The latest version of the ARMv7 vector floating-point extensions,
    including hardware support for fused multiple accumulate. D16 or D32
    variants may be implemented.

- Integer divide:
    The SDIV and UDIV instructions provide signed and unsigned integer
    division in hardware. When implemented, these instructions may be
    available in either both Thumb and ARM, or Thumb only.

This patch adds new HWCAP defines to describe these new features. The
integer divide capabilities are split into two bits for ARM and Thumb
respectively. Whilst HWCAP_IDIVA should never be set if HWCAP_IDIVT is
clear, separating the bits makes it easier to interpret from userspace.
Signed-off-by: Will Deacon <will.deacon@arm.com>

254cdf8e

ARM: hwcaps: use shifts instead of hardcoded constants · 194a7f72

Will Deacon authored Jun 03, 2011

The HWCAP numbers are defined as constants, each one being a power of 2.
This has become slightly unwieldy now that we have reached 32k.

This patch changes the HWCAP defines to use (1 << n) instead of coding
the constant directly. The values remain unchanged.
Signed-off-by: Will Deacon <will.deacon@arm.com>

194a7f72

Merge branch 'arm/proc-macros' of git://git.linaro.org/people/dmart/linux-2.6-arm into for-rmk · 305edadb
Will Deacon authored Jul 07, 2011

305edadb
ARM: mm: tlb-v7: Use the new processor struct macros · 2ba564b9
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
2ba564b9
ARM: mm: tlb-v6: Use the new processor struct macros · 3b7f39fa
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
3b7f39fa
ARM: mm: tlb-v4wbi: Use the new processor struct macros · ca560963
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
ca560963
ARM: mm: tlb-v4wb: Use the new processor struct macros · 2284ece2
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
2284ece2
ARM: mm: tlb-v4: Use the new processor struct macros · f249a642
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
f249a642
ARM: mm: tlb-v3: Use the new processor struct macros · d7b84d24
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
d7b84d24
ARM: mm: tlb-fa: Use the new processor struct macros · 27eebe4c
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
27eebe4c

ARM: mm: proc-xscale: Use new generic struct definition macros · ab1a746d

Dave Martin authored Jun 23, 2011

Without this patch, xscale_80200_A0_A1 is missing the
icache_flush_all entry, which would result in the wrong functions
being called at run-time.

This patch re-uses xscale_icache_flush_all for
xscale_80200_A0_A1_cache_fns.
Signed-off-by: Dave Martin <dave.martin@linaro.org>

ab1a746d

ARM: mm: proc-xsc3: Use new generic struct definition macros · c21898f9
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
c21898f9
ARM: mm: proc-v7: Use the new processor struct macros · 78a8f3c3
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
78a8f3c3
ARM: mm: proc-v6: Use the new processor struct macros · 7b7dc6e8
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
7b7dc6e8
ARM: mm: proc-sa1100: Use the new processor struct macros · f58d59f6
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
f58d59f6
ARM: mm: proc-sa110: Use the new processor struct macros · 5973ba58
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
5973ba58

ARM: mm: proc-mohawk: Use the new processor struct macros · a39a3218

Dave Martin authored Jun 23, 2011

This patch also defines a suitable flush_icache_all implementation
which would otherwise be missing, resulting in a link failure.
Thanks to Nicolas Pitre for suggesting the code for this.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>

a39a3218

ARM: mm: proc-feroceon: Use the new processor struct macros · e43b670e
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
```
e43b670e
ARM: mm: proc-fa526: Use the new processor struct macros · d6ed10ce
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
d6ed10ce
ARM: mm: proc-arm9tdmi: Use the new processor struct macros · b4a19f03
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
b4a19f03
ARM: mm: proc-arm946: Use the new processor struct macros · b1b9892b
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
b1b9892b
ARM: mm: proc-arm940: Use the new processor struct macros · b3755801
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
b3755801
ARM: mm: proc-arm926: Use the new processor struct macros · be90da45
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
be90da45
ARM: mm: proc-arm925: Use the new processor struct macros · 6c240aec
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
6c240aec
ARM: mm: proc-arm922: Use the new processor struct macros · f3e7383f
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
f3e7383f
ARM: mm: proc-arm920: Use the new processor struct macros · 68f5e1ac
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
68f5e1ac
ARM: mm: proc-arm7tdmi: Use the new processor struct macros · fd10e272
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
fd10e272
ARM: mm: proc-arm740: Use the new processor struct macros · 4cc1f0fa
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
4cc1f0fa
ARM: mm: proc-arm720: Use the new processor struct macros · 449870b1
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
449870b1
ARM: mm: proc-arm6_7: Use the new processor struct macros · c3be06eb
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
c3be06eb
ARM: mm: proc-arm1026: Use the new processor struct macros · 5c9369bc
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
5c9369bc
ARM: mm: proc-arm1022: Use the new processor struct macros · f2d8cae1
Dave Martin authored Jun 23, 2011
```
Signed-off-by: Dave Martin <dave.martin@linaro.org>
```
f2d8cae1