- 06 Feb, 2020 36 commits
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Isabel Zhang authored
[Why] Starting from 14nm, the PLL is built into the PHY and the PLL is mapped to PHY on 1 to 1 basis. In the code, the DP port is mapped to a PLL that was not initialized. This causes DP to HDMI dongle to not light up the display. [How] Initializations added for PLL2 when creating resources. Signed-off-by:
Isabel Zhang <isabel.zhang@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tony Cheng authored
[Why] these registers should have been double buffered. SW workaround we will have SW program the more aggressive (lower) values whenever we are upating this register, so we will not have underflow at expense of less optimzal request pattern. [How] there is a driver bug where we don't check for 0, which is uninitialzed HW default. since 0 is smaller than any value we need to program, driver end up with not programming these registers Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Hersen Wu authored
[Why] old panel has been enabled for window driver but not linux. [How] enable oled panel support for linux. this patch is dc part. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Reviewed-by:
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Jing Zhou authored
[why] Resume from modern standby, edp stream disabled but abm keep enabled. External monitor select OTG source 0 which ABM enabled. [how] Disable abm before disable crtc when reset path mode not call core link disable stream. Signed-off-by:
Jing Zhou <Jing.Zhou@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] The DMUB tracebuffer is useful for understanding DMCUB execution state. [How] Add a "show" attribute debugfs so we can loop through the buffer and print the entries. The structs for the entry format are defined in the debugfs since the tracebuffer header no longer exists in the DMUB service. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
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Yongqiang Sun authored
[Why] Underflow is observed when plug in a 4K@60 monitor with 1366x768 eDP due to DPPCLK is too low. [How] Limit minimum DPPCLK to 100MHz. Signed-off-by:
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David Galiffi authored
[WHY] enum dc_log_type has more than 32 entries. User cannot set larger entries, like LOG_DSC. Logs from LOG_GAMMA_DEBUG where being printed even though flag was not enabled, because dal_logger_should_log check erroneously passed. [HOW] Change struct dal_logger.mask and struct dc_init_data.mask to uint64_t. Signed-off-by:
David Galiffi <David.Galiffi@amd.com> Reviewed-by:
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Sung Lee authored
[WHY & HOW] Having watermark ranges saved inside clk_mgr to be available for debug at all times would be useful. Add it to the clk_mgr_internal struct for reference. Only populated for Renoir, unused for other asics. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
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Yongqiang Sun authored
[Why] hyperV flag should be passed from dm to DC, and override the nv12 flip workaround flag. [How] Add flag to phy address config struct and pass the value in dm. Signed-off-by:
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Eric Yang authored
[Why] Previous logic is only good for 15W parts. Other configuration need a smarter logic to match clk levels with pp table in the fuse. [How] Cache all 8 DPM level's clock data, find lvl that match each pstate in the pp table and build input into DML base on that Signed-off-by:
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Wenjing Liu authored
[why] hwss should not guess what type of pipe lock is needed. The caller of the lock function should know the right type of pipe lock. Decouple the setup of global lock outside of pipe control lock logic. Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
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Aric Cyr authored
[Why] Engine can be NULL in some cases, so we must not acquire it. [How] Check for NULL engine before acquiring. Signed-off-by:
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Sung Lee authored
[WHY & HOW] Previously drain clk was unconstrained and fill clk was constrained on fclk. We want to change it to fill clk unconstrained and drain clock constrained to dcfclk. Signed-off-by:
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Charlene Liu authored
[why] new HW engine mapping requirment use in PSP [how] report stream_enc_inst Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
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Peikang Zhang authored
Description for DCHUBBUB_TEST_DEBUG_DATA is changed to avoid any future confusions. Signed-off-by:
Peikang Zhang <peikang.zhang@amd.com> Reviewed-by:
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Roman Li authored
[Why] The break in apply_ctx_interdependent_lock() may potentially lead to early break from the loop leaving update plane unlocked [How] Remove break Signed-off-by:
Roman Li <roman.li@amd.com> Reviewed-by:
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Peikang Zhang authored
[Why] int i can go out of boundary which will cause crash [How] Fixed the maximum value of i to avoid i going out of boundary Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
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Aric Cyr authored
Signed-off-by:
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Aric Cyr authored
[Why] After locking refactor GSL is not acquired properly resulting in immediate flip issues. [How] Do not copy old GSL state anymore since GSL is acquired earlier now. Signed-off-by:
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Anthony Koo authored
[Why] Screen flickering when HDR switches between FP16 and ARGB2101010 [How] Moved pipe_control_lock so stream update and plane update occur atomically Signed-off-by:
Lucy Li <lucy.li@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] The DMCUB may be currently executing commands when the reset is triggered. Before issuing a reset we should first wait for the DMCUB to finish its work. [How] Send the GPINT command for halting the firmware before reset. Get the ack for the command then wait for the scratch register to become the correct value. We want this to take under ~40us or so at most before we force reset to cover PHY delay sequence max time. Each register read will be at least ~1-3us so don't bother using udelay. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] The General Purpose Interrupt is used on the DMCUB to pass lightweight commands via a register to the DMCUB. This is limited to 32-bit command and 32-bit response. This will be used for shutting down the firmware in a clean manner. [How] Add the command IDs and the data register to correctly format the commands. Add the interface functions to dmub_srv for sending and receiving the commands. Signed-off-by:
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Eric Bernstein authored
[Why] Diagnostics team reported various issues found when enabling warnings as errors [How] Fix implicit conversions Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Anthony Koo authored
[Why] DSC updates only set type to FULL UPDATE, but doesn't flag the change [How] Add DSC flag update flag Signed-off-by:
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Anthony Koo authored
[Why] Eventually want to lock at a higher level in stack. To do this, we need to be able to isolate the parts that need to be done after pipe unlock. [How] Split out programming that is done post unlock. Signed-off-by:
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Sung Lee authored
[WHY] The optimized_require flag is needed to set watermarks and clocks lower in certain conditions. This flag is set to true and then set to false while programming front end in dcn20. [HOW] Do not set the flag to false while disabling plane. Signed-off-by:
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Roman Li authored
[Why] Driver crash with psr feature enabled due to divide-by-zero error. This is a regression after rework to calculate static screen frame number entry time. [How] Correct order of operations to avoid divide-by-zero. Signed-off-by:
Zhan Liu <Zhan.Liu@amd.com> Acked-by:
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Joseph Gravenor authored
[why/how] We found out that the register we read actually gets reset by SMU after we loose power, meaning this always returns true Signed-off-by:
Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by:
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George Shen authored
[Why] The call to dp_enable_link_phy are using default/invalid values for clock id and link settings. [How] Move workaround code to after its parameter variables are determined. Signed-off-by:
George Shen <george.shen@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] Must know psr version during runtime. [How] Add set psr version message structures. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Hawking Zhang authored
For sriov, psp ip block has to be initialized before ih block for the dynamic register programming interface that needed for vf ih ring buffer. On the other hand, current psp ip block hw_init function will initialize xgmi session which actaully depends on interrupt to return session context. This results an empty xgmi ta session id and later failures on all the xgmi ta cmd invoked from vf. xgmi ta session initialization has to be done after ih ip block hw_init call. to unify xgmi session init/fini for both bare-metal sriov virtualization use scenario, move xgmi ta init to xgmi_add_device call, and accordingly terminate xgmi ta session in xgmi_remove_device call. The existing suspend/resume sequence will not be changed. v2: squash in return fix from Nirmoy Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Frank Min <Frank.Min@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
Call the cmd ids for set/get srm according to the sysfs call v2: Use define for the magic number Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
[Why] we need to load SRM before we start HDCP. Because for S3 case the sysfs call will be after we have already enabled HDCP, so we might not be using the latest SRM [How] Set srm before starting HDCP. Signed-off-by:
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Bhawanpreet Lakha authored
[Why] PSP doesn't have the ability to store SRM in a non-volatile memory. And since the kernel cannot write to the storage directly, we need usermode to facilitate this As per spec the SRM needs to be persistent so this interface is to be called by the usermode anytime the system goes down/powers on *boot/resume: load from storage *shutdown/suspend: save to storage [How] Provide a sysfs interface so that the usermode can set/get srm at the right times save to storage: call "cat /sys/class/drm/card0/device/hdcp_srm > file" after boot and resume -driver calls psp_get_srm() to get the stored srm and outputs it load from storage: call "cat file > /sys/class/drm/card0/device/hdcp_srm" before shutdown and suspend -driver reads the file from sysfs and calls psp_set_srm() to send the SRM to PSP v2: -update commit description -add comment about sysfs file handling in the code v3: - squash in use after free fix (Dan Carpenter) Signed-off-by:
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- 05 Feb, 2020 4 commits
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Bhawanpreet Lakha authored
[Why] We need to support SRM(System Renewability Message) As per hdcp spec (5.Renewability) SRM needs to be storage in a non-volatile memory. PSP owns the checking of SRM but doesn't have the ability to store it in a non-volatile memory. So we need the kernel driver to facilitate it using the interface provided by PSP [How] Add the interface to the header file, so the driver can use them v2: update commit description Signed-off-by:
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Bhawanpreet Lakha authored
[Why] We need this to create sysfs (followup patch) [How] Change the parameter Signed-off-by:
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Christian König authored
If provided we only sync to the BOs reservation object and no longer to the root PD. v2: update comment, cleanup amdgpu_bo_sync_wait_resv v3: use correct reservation object while clearing v4: fix typo in amdgpu_bo_sync_wait_resv Signed-off-by:
Christian König <christian.koenig@amd.com> Tested-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Christian König authored
No matter what we always need to sync to moves. Signed-off-by:
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