- 20 Oct, 2020 1 commit
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Hou Zhiqiang authored
NXP Layerscape (ls1028a, ls2088a), dra7xxx and imx6 platforms are either programmed or statically configured to forward the error triggered by a link-down state (eg no connected endpoint device) on the system bus for PCI configuration transactions; these errors are reported as an SError at system level, which is fatal. Enumerating a PCI tree when the PCIe link is down is not sensible either, so even if the link-up check is racy (link can go down after map_bus() is called) add a link-up check in map_bus() to prevent issuing configuration transactions when the link is down. SError report: SError Interrupt on CPU2, code 0xbf000002 -- SError CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.9.0-rc5-next-20200914-00001-gf965d3ec86fa #67 Hardware name: LS1046A RDB Board (DT) pstate: 20000085 (nzCv daIf -PAN -UAO BTYPE=--) pc : pci_generic_config_read+0x3c/0xe0 lr : pci_generic_config_read+0x24/0xe0 sp : ffff80001003b7b0 x29: ffff80001003b7b0 x28: ffff80001003ba74 x27: ffff000971d96800 x26: ffff00096e77e0a8 x25: ffff80001003b874 x24: ffff80001003b924 x23: 0000000000000004 x22: 0000000000000000 x21: 0000000000000000 x20: ffff80001003b874 x19: 0000000000000004 x18: ffffffffffffffff x17: 00000000000000c0 x16: fffffe0025981840 x15: ffffb94c75b69948 x14: 62203a383634203a x13: 666e6f635f726568 x12: 202c31203d207265 x11: 626d756e3e2d7375 x10: 656877202c307830 x9 : 203d206e66766564 x8 : 0000000000000908 x7 : 0000000000000908 x6 : ffff800010900000 x5 : ffff00096e77e080 x4 : 0000000000000000 x3 : 0000000000000003 x2 : 84fa3440ff7e7000 x1 : 0000000000000000 x0 : ffff800010034000 Kernel panic - not syncing: Asynchronous SError Interrupt CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.9.0-rc5-next-20200914-00001-gf965d3ec86fa #67 Hardware name: LS1046A RDB Board (DT) Call trace: dump_backtrace+0x0/0x1c0 show_stack+0x18/0x28 dump_stack+0xd8/0x134 panic+0x180/0x398 add_taint+0x0/0xb0 arm64_serror_panic+0x78/0x88 do_serror+0x68/0x180 el1_error+0x84/0x100 pci_generic_config_read+0x3c/0xe0 dw_pcie_rd_other_conf+0x78/0x110 pci_bus_read_config_dword+0x88/0xe8 pci_bus_generic_read_dev_vendor_id+0x30/0x1b0 pci_bus_read_dev_vendor_id+0x4c/0x78 pci_scan_single_device+0x80/0x100 Link: https://lore.kernel.org/r/20200916054130.8685-1-Zhiqiang.Hou@nxp.comSigned-off-by:
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [lorenzo.pieralisi@arm.com: rewrote the commit log, remove Fixes tag] Signed-off-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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- 13 Oct, 2020 6 commits
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Jisheng Zhang authored
Currently, dw_pcie_msi_init() allocates and maps page for msi, then program the PCIE_MSI_ADDR_LO and PCIE_MSI_ADDR_HI. The Root Complex may lose power during suspend-to-RAM, so when we resume, we want to redo the latter but not the former. If designware based driver (for example, pcie-tegra194.c) calls dw_pcie_msi_init() in resume path, the msi page will be leaked. As pointed out by Rob and Ard, there's no need to allocate a page for the MSI address, we could use an address in the driver data. To avoid map the MSI msg again during resume, we move the map MSI msg from dw_pcie_msi_init() to dw_pcie_host_init(). Suggested-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201009155505.5a580ef5@xhacker.debianSigned-off-by:
Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by:
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Jisheng Zhang authored
If MSI is disabled, there's no need to program PCIE_MSI_INTR0_MASK and PCIE_MSI_INTR0_ENABLE registers. Link: https://lore.kernel.org/r/20201009155436.27e67238@xhacker.debianSigned-off-by:
Gustavo Pimentel <gustavo.pimentel@synopsys.com>
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Kunihiko Hayashi authored
After applying "PCI: dwc: Add common iATU register support", there is no need to set own iATU in the Keystone driver itself. Suggested-by:
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by:
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Kunihiko Hayashi authored
This gets iATU register area from reg property that has reg-names "atu". In Synopsys DWC version 4.80 or later, since iATU register area is separated from core register area, this area is necessary to get from DT independently. Suggested-by:
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Kunihiko Hayashi authored
In the dt-bindings, "atu" reg-names is required to get the register space for iATU in Synopsis DWC version 4.80 or later. Link: https://lore.kernel.org/r/1601444167-11316-3-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by:
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Kunihiko Hayashi authored
In the dt-bindings, "atu" reg-names is required to get the register space for iATU in Synopsys DWC version 4.80 or later. Link: https://lore.kernel.org/r/1601444167-11316-2-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by:
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- 28 Sep, 2020 1 commit
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Gustavo Pimentel authored
Fixes warning given by executing "make C=2 drivers/pci/" Sparse output: CHECK drivers/pci/controller/dwc/pcie-designware.c drivers/pci/controller/dwc/pcie-designware.c:432:52: warning: cast truncates bits from constant value (ffffffff7fffffff becomes 7fffffff) Link: https://lore.kernel.org/r/7ea7f7d342f97c758949a17b870012f52ce5b3f5.1600767645.git.gustavo.pimentel@synopsys.comReported-by:
Bjorn Helgaas <bhelgaas@google.com> Signed-off-by:
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- 24 Sep, 2020 2 commits
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Hou Zhiqiang authored
The commit 0a121f9b ("misc: pci_endpoint_test: Use streaming DMA APIs for buffer allocation") changed to use streaming DMA APIs, however, dma_map_single() might not return a 4KB aligned address, so add the default_data as driver data for Layerscape PCIe controllers to make it 4KB aligned. Link: https://lore.kernel.org/r/20200918080024.13639-13-Zhiqiang.Hou@nxp.comSigned-off-by:
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Xiaowei Bao authored
Add LS1088a in pci_device_id table so that pci-epf-test can be used for testing PCIe EP in LS1088a. Link: https://lore.kernel.org/r/20200918080024.13639-12-Zhiqiang.Hou@nxp.comSigned-off-by:
Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by:
Andrew Murray <andrew.murray@arm.com>
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- 21 Sep, 2020 9 commits
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Xiaowei Bao authored
Add PCIe EP mode support for ls1088a and ls2088a, there are some difference between LS1 and LS2 platform, so refactor the code of the EP driver. Link: https://lore.kernel.org/r/20200918080024.13639-10-Zhiqiang.Hou@nxp.comSigned-off-by:
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Xiaowei Bao authored
dw_pcie_ep_raise_msix_irq was never called in the exisitng driver before, because the ls1046a platform don't support the MSIX feature and msix_capable was always set to false. Now that add the ls1088a platform with MSIX support, use the doorbell method to support the MSIX feature. Link: https://lore.kernel.org/r/20200918080024.13639-9-Zhiqiang.Hou@nxp.comSigned-off-by:
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Xiaowei Bao authored
The different PCIe controller in one board may be have different capability of MSI or MSIX, so change the way of getting the MSI capability, make it more flexible. Link: https://lore.kernel.org/r/20200918080024.13639-8-Zhiqiang.Hou@nxp.comSigned-off-by:
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Xiaowei Bao authored
Fix some format issue of the code in EP driver. Link: https://lore.kernel.org/r/20200918080024.13639-7-Zhiqiang.Hou@nxp.comSigned-off-by:
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Xiaowei Bao authored
Add compatible strings for ls1088a and ls2088a. Link: https://lore.kernel.org/r/20200918080024.13639-6-Zhiqiang.Hou@nxp.comSigned-off-by:
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Xiaowei Bao authored
Each PF of EP device should have its own MSI or MSIX capabitily struct, so create a dw_pcie_ep_func struct and move the msi_cap and msix_cap to this struct from dw_pcie_ep, and manage the PFs via a list. Link: https://lore.kernel.org/r/20200918080024.13639-5-Zhiqiang.Hou@nxp.comSigned-off-by:
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Xiaowei Bao authored
Move the function of getting MSI capability to the front of init function, because the init function of the EP platform driver will use the return value by the function of getting MSI capability. Link: https://lore.kernel.org/r/20200918080024.13639-4-Zhiqiang.Hou@nxp.comSigned-off-by:
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Xiaowei Bao authored
Add the doorbell mode of MSI-X in DWC EP driver. Link: https://lore.kernel.org/r/20200918080024.13639-3-Zhiqiang.Hou@nxp.comSigned-off-by:
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Xiaowei Bao authored
Add multiple PFs support for DWC, due to different PF have different config space, we use func_conf_select callback function to access the different PF's config space, the different chip company need to implement this callback function when use the DWC IP core and intend to support multiple PFs feature. Link: https://lore.kernel.org/r/20200918080024.13639-2-Zhiqiang.Hou@nxp.comSigned-off-by:
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- 10 Sep, 2020 7 commits
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Rob Herring authored
Convert the remaining cases of register accesses using dbi_base rather than dw_pcie_(read|write)[bwl]_dbi accessors. Link: https://lore.kernel.org/r/20200821035420.380495-41-robh@kernel.orgSigned-off-by:
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Rob Herring authored
The Designware controller has common registers to set number of fast training sequence ordered sets. The Artpec6, Intel, and Tegra driver initialize these register fields. Let's move the initialization to the common setup code and drivers just have to provide the value. There's a slight change in that the common clock mode N_FTS field is now initialized. Previously only the Intel driver set this. It's not clear from the code if common clock mode is used in the Artpec6 or Tegra driver. It depends on the DWC configuration. Given the field is not initialized while the others are, it seems unlikely common clock mode is used. Link: https://lore.kernel.org/r/20200821035420.380495-40-robh@kernel.orgSigned-off-by:
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Rob Herring authored
'max_width' is read, but never used, so let's remove it. Link: https://lore.kernel.org/r/20200821035420.380495-39-robh@kernel.orgSigned-off-by:
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Rob Herring authored
The PCI_CAP_ID_EXP offset is only needed by intel_pcie_link_setup(), so let's retrieve it there and avoid storing the offset. Link: https://lore.kernel.org/r/20200821035420.380495-38-robh@kernel.orgSigned-off-by:
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Rob Herring authored
A driver doesn't need to check for DT 'device_type' property, so let's remove the check. Link: https://lore.kernel.org/r/20200821035420.380495-37-robh@kernel.orgSigned-off-by:
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Rob Herring authored
The Intel driver is the only one to set PORT_LINK_DLL_LINK_EN. The default value is set and it seems pretty certain that enabling link initialization is always required. Maybe it could just be dropped from the Intel driver, but lets move setting it into the common code to be sure. Link: https://lore.kernel.org/r/20200821035420.380495-36-robh@kernel.orgSigned-off-by:
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Rob Herring authored
keystone would force gen2 if no DT property. Now it relies on the PCI_EXP_LNKCAP value. Link: https://lore.kernel.org/r/20200821035420.380495-35-robh@kernel.orgSigned-off-by:
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- 08 Sep, 2020 14 commits
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Rob Herring authored
The ATU registers are only accessed in pcie-designware.c and can be private to it. Link: https://lore.kernel.org/r/20200821035420.380495-34-robh@kernel.orgSigned-off-by:
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Rob Herring authored
The DBI2 appears to be write-only and there's no read accesses in the code anyways, so let's remove all the read_dbi2 related code. Link: https://lore.kernel.org/r/20200821035420.380495-33-robh@kernel.orgSigned-off-by:
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Rob Herring authored
The Tegra driver has its own defines for common Designware Port Logic registers. Convert it to use the standard register definitions. Link: https://lore.kernel.org/r/20200821035420.380495-32-robh@kernel.orgSigned-off-by:
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Rob Herring authored
While the Designware controller appears to hard code the PCI_CAP_ID_EXP capability register at 0x70, there's no need to hard code this in the driver as it is discoverable. Link: https://lore.kernel.org/r/20200821035420.380495-31-robh@kernel.orgSigned-off-by:
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Rob Herring authored
The QCom driver has its own defines for common PCI config space registers. It also hard codes the capability register offsets which are discoverable. Convert it to use the standard register definitions. Link: https://lore.kernel.org/r/20200821035420.380495-30-robh@kernel.orgSigned-off-by:
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Rob Herring authored
The i.MX6 driver has its own defines for common PCI config space registers. It also hard codes the capability register offsets which are discoverable. Convert it to use the standard register definitions. Link: https://lore.kernel.org/r/20200821035420.380495-29-robh@kernel.orgSigned-off-by:
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Rob Herring authored
The meson 'elbi' registers are just the Designware 'dbi' space and all the registers accessed are either standard PCI config space or DWC port logic registers. Convert the accesses to use the common defines and register accessors. Link: https://lore.kernel.org/r/20200821035420.380495-28-robh@kernel.orgSigned-off-by:
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Rob Herring authored
The common Designware init already initializes the RC PCI_COMMAND, BAR0 and BAR1 registers. The only difference here is the common code sets SERR. If clearing SERR is what's desired, then the Meson driver should do that instead. Link: https://lore.kernel.org/r/20200821035420.380495-27-robh@kernel.orgSigned-off-by:
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Rob Herring authored
The meson lanes initialization is the same DWC port logic registers as in dw_pcie_setup(). We just need to initialize 'num_lanes' to 1 to do the same init. dw_pcie_setup_rc() sets the PORT_LOGIC_SPEED_CHANGE bit, so setting it can be dropped. Link: https://lore.kernel.org/r/20200821035420.380495-26-robh@kernel.orgSigned-off-by:
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Rob Herring authored
"Fast Link Mode" is a simulation environment speed up setting which should never be set and the default is not set. However some Amlogic platforms have it set (by firmware presumably). See commit 87dccf09 ("PCI: amlogic: meson: Don't use FAST_LINK_MODE to set up link") for more information. Let's clear it in core DWC code so we can drop some vendor specific code. Link: https://lore.kernel.org/r/20200821035420.380495-25-robh@kernel.orgSigned-off-by:
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Rob Herring authored
Add a 'num_lanes' field to allow drivers to provide a the number of lanes if not in DT or using a custom DT property. A driver can provide a non-zero value which is used if the DT doesn't have a 'num-lanes' property. Link: https://lore.kernel.org/r/20200821035420.380495-24-robh@kernel.orgSigned-off-by:
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Rob Herring authored
PCIE_LINK_WIDTH_SPEED_CONTROL is already defined in pcie-designware.h, so remove it from the i.MX6 driver. Link: https://lore.kernel.org/r/20200821035420.380495-23-robh@kernel.orgSigned-off-by:
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Rob Herring authored
Move the IS_ENABLED(CONFIG_PCI_MSI) check into dw_pcie_msi_init() instead of duplicating it in all the drivers. Link: https://lore.kernel.org/r/20200821035420.380495-22-robh@kernel.orgSigned-off-by:
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Rob Herring authored
The DWC core driver already parses and stores the 'num-viewport' DT property, so there is no need for the Keystone driver to store it. Link: https://lore.kernel.org/r/20200821035420.380495-21-robh@kernel.orgSigned-off-by:
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