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- 11 Sep, 2023 2 commits
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Wenjing Liu authored
[why] We have a few cases where we need to perform update topology update in dc update interface. However some of the updates are not seamless This could cause user noticible glitches. To enforce seamless transition we are adding a checking condition and error logging so the corruption as result of non seamless transition can be easily spotted. Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
Stylon Wang <stylon.wang@amd.com> Signed-off-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alvin Lee authored
[Description] Before enabling the phantom OTG for an update we must enable DPG to avoid underflow. Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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- 30 Aug, 2023 1 commit
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SungHuai Wang authored
[WHY] OTG_STATIC_SCREEN_EVENT_MASK is changed in DCN3, but we still follow DCN2 to apply setting for OTG_STATIC_SCREEN_EVENT_MASK. [How] Add new function to apply correct settings for DCN3 series. Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Acked-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
SungHuai Wang <danny.wang@amd.com> Tested-by:
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- 23 Jun, 2023 1 commit
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Alvin Lee authored
- DC mode clock switch interface was previously only executed for DCN303. Enable it for DCN32x so that the interface is called correctly - Assign function pointers for DCN32x that are used in the dc mode interface - Update the dc mode interface to work generically for each ASIC - In update_clocks, make sure to consider softmax if we're in DC mode Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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- 09 Jun, 2023 4 commits
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Alvin Lee authored
[Description] - Refactor HW sequencer to use a build / execute sequence - Also move gamma updates to become fast v2: squash in build fix ("drm/amd/display: Fix guarding of 'if (dc->debug.visual_confirm)'") Acked-by: -
Saaem Rizvi authored
[WHY and HOW] Currently, on DCN32 we have an old workaround to resolve a DIO FIFO speed issue when writing to the OTG DIVIDER register. However, this workaround is not safe as we should be applying the DIO FIFO rampup logic when the OTG re disabled along with the encoders. This new workaround accounts for this. If the workaround sequence is incorrect, like it is was, there is a chance we might hang. this new workaround was first implemented in DCN314. Reviewed-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Saaem Rizvi <syedsaaem.rizvi@amd.com> Tested-by:
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Qingqing Zhuo authored
[Why] Drop dead code for Linux. [How] Remove all IS_FPGA_MAXIMUS_DC and IS_DIAG_DC Reviewed-by:
Ariel Bernstein <eric.bernstein@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by:
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Leo (Hanghong) Ma authored
[Why && How] We would like to have visual confirm color support for MCLK switch. 1. Set visual confirm color to yellow: Vblank MCLK switch. 2. Set visual confirm color to cyan: FPO + Vblank MCLK switch. 3. Set visual confirm color to pink: Vactive MCLK switch. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Tested-by:
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- 31 Mar, 2023 1 commit
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Alvin Lee authored
[Description] * Pass in pipe index for FPO cmd to DMCUB - This change will pass in the pipe index for each stream that is using FPO - This change is in preparation to enable FPO + VActive * Use per pipe P-State force for FPO - For FPO, instead of using max watermarks value for P-State disallow, use per pipe p-state force instead - This is in preparation to enable FPO + VActive Reviewed-by:
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- 07 Mar, 2023 1 commit
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Alvin Lee authored
[Description] For pipe harvesting cases we cannot rely on array index to get the correct OPP instance, we must loop through each instance to find the correct one. Reviewed-by:
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- 16 Feb, 2023 1 commit
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Arthur Grillo authored
Add includes that were previously missing to reduce the number of -Wmissing-prototypes warnings. Signed-off-by:
Arthur Grillo <arthurgrillo@riseup.net> Signed-off-by:
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- 02 Feb, 2023 1 commit
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George Shen authored
[Why] The hwss function does_plane_fit_in_mall not applicable to dcn3.2 asics. Using it with dcn3.2 can result in undefined behaviour. [How] Assign the function pointer to NULL. Reviewed-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
George Shen <george.shen@amd.com> Tested-by:
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- 31 Jan, 2023 1 commit
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George Shen authored
[Why] The hwss function does_plane_fit_in_mall not applicable to dcn3.2 asics. Using it with dcn3.2 can result in undefined behaviour. [How] Assign the function pointer to NULL. Reviewed-by:
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- 03 Jan, 2023 1 commit
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Alvin Lee authored
[Description] - Proper phantom pipe disable sequence was missing in commit_planes_for_stream - If disabling phantom pipe, turn on phantom OTG first, and turn off the phantom OTG after the plane is disabled - Also update sequence for enabling / disabling phantom streams (apply_ctx_to_hw). When enabling phantom pipes, enable before doing front end programming for phantom pipes. If disabling phantom pipes, disable after front end programming (i.e. after phantom plane disable) - TODO: Still need to properly handle transition case when a phantom pipe is transitioned directly into a real pipe (need to fully disable the phantom pipe first) Acked-by:
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- 15 Nov, 2022 1 commit
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Alvin Lee authored
[Description] - When transitioning a pipe in use (non-phantom) to become a phantom pipe, we must fully disable the pipe first before doing any phantom pipe programming - Move phantom OTG enablement to after "regular" front-end programming sequence (including wait for vupdate) - If a pipe is being transitioned into a phantom pipe, fully disable it first Reviewed-by:
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- 29 Sep, 2022 1 commit
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Dillon Varone authored
[Why&How] Several transitions were fixed that will allow Dynamic ODM and MPO transitions to be supported on DCN32. 1) Due to resource limitations, in certain scenarios that require an MPO plane to be split, the features cannot be combined with the current policy. This is due to unsafe transitions being required (OPP instance per MPCC being switched on active pipe is not supported by DCN), to support the split plane with ODM active as it moves across the viewport. Dynamic ODM will now be disabled when MPO is required. 2) When exiting MPO and re-entering ODM, DC assigns an inactive pipe for the next ODM pipe, which under previous power gating policy would result in programming a gated DSC HW block. New policy dynamically gates/un-gates DSC blocks when Dynamic ODM is active to support transitions on DCN32 only. 3) Entry and exit from 3 plane MPO and Dynamic ODM requires a minimal transition so that all pipes which require their MPCC OPP instance to be changed have a full frame to be disabled before reprogramming. To solve this, the Dynamic ODM policy now utilizes minimal state transitions when entering or exiting 3 plane scenarios. 4) Various fixes to DCN32 pipe merge/split algorithm to support Dynamic ODM and MPO transitions. In summary, this commit fixes various transitions to support ODM->MPO and MPO->ODM. Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Reviewed-by:
Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by:
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- 19 Sep, 2022 1 commit
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Wenjing Liu authored
[why] Original change 594b237b ("drm/amd/display: Add interface to track PHY state") was implemented by assuming stream's dpms off is equivalent to PHY power off. This assumption doesn't hold in following situations: 1. MST multiple stream scenario, where multiple streams are sharing the same PHY output. Toggle dpms off for one of the stream doesn't power off the PHY due to the presence of other streams. 2. enable stream failure scenario, where enable stream fails due to failure of link training. This will cause DPMS off is set to false, while the actual PHY power state is off in certain cases. Due to the problematic assumption, the logic will skip disabling other streams for MST multiple stream scenario, therefore PHY is not actually powered off. [how] 1. Rework this refactor by moving PHY state update down to hardware level, where we update PHY state in place when hardware sequencer is actually changing the power state of the PHY hardware. 2. Reimplement symclk on TX off workaround in place when we are actually calling transmitter control to power off PHY in dcn32. Note the workaround is added due to the lack of proper software interface to set TX while keeping symclk on. We plan to address this interface problem so we can set TX off only without affecting symclk in future dcn versions. Fixes: 594b237b ("drm/amd/display: Add interface to track PHY state") Reviewed-by:
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- 13 Sep, 2022 1 commit
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Alvin Lee authored
[Description] In some cases the viewport position of the main pipes can change without triggering a full update. In this case the subvp phantom viewports must be updated accordingly. Tested-by:
Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by:
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- 25 Aug, 2022 1 commit
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Alvin Lee authored
[Why] Sometimes pixel clock needs to remain active after transmitter disable. [How] Use update_phy_state to track PHY state after stream enable/disable and program pixel clock as needed. Reviewed-by:
Brian Chang <Brian.Chang@amd.com> Signed-off-by:
Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by:
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- 05 Jul, 2022 5 commits
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Alvin Lee authored
[Why] Newer DCN should use optc3 [How] Declare optc3 vmin/vmax function in header. Signed-off-by:
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Samson Tam authored
[Why] Most of the time, a single display uses the ODM combine. When using multi-display, we use ODM combine only if it is necessary. These cases are not flexible enough for us, and we can improve them to take advantage of our hardware. We want to have more control over the ODM policy. [How] This commit add a new debug flag named enable_single_display_2to1_odm_policy to control the ODM policy and another flag named enable_dp_dig_pixel_rate_div_policy to fine control the ODM combine. This is possible by adding a new "pipe.dest" parameter that can be set to ODM 2:1 combined if we use a single display. For dynamic ODM combine, when using DP-DIG, DCN applies K2=2 settings for ODM combine. Note that this feature affects the following registers: - timing.pix_clk_100khz -> DP_VID_M, DP_VID_N - requested_pix_clk_100hz -> DP_DTOn_PHASE - OTGn_PIXEL_RATE_DIVK2 - DP_PIXEL_PER_CYCLE_PROCESSING_MODE - DIG_FIFO_OUTPUT_PIXEL_MODE - DP_VID_N_MUL Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Eric Bernstein authored
Add function to set pixels per cycle in DIG stream encoder Acked-by:
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Martin Leung authored
[WHY]: Lut pipeline will be hooked up differently in some asics need to add new interfaces and missing registers. [HOW]: Add missing registers and hook up programming from DPP for pre-blend lut. Acked-by:
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Alvin Lee authored
This commit enables the SubVP feature. To achieve that, we need to: - Don't force p-state disallow on SubVP (can't block dummy p-state) - Send calculated watermark to DMCUB for SubVP - Adjust CAB mode message to PMFW - Add a proper locking sequence for SubVP - Various fixes to SubVP static analysis and determining SubVP config - Currently SubVP not supported with pipe split so merge all pipes before setting up SubVp Reviewed-by:
Alan Liu <HaoPing.Liu@amd.com> Signed-off-by:
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- 03 Jun, 2022 2 commits
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Jun Lei authored
[why] New dividers in DCCG need to be programmed depending on encoder/stream type since pixels per clock in OTG/DIO is different DIO also needs additional programming depending on pixels per clock Signed-off-by:
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Aurabindo Pillai authored
Add core DC support for DCN 3.2.x. v2: squash in fixup (Alex) Signed-off-by:
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- 25 Jan, 2022 1 commit
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Aric Cyr authored
Tested-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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- 18 Jan, 2022 1 commit
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Felipe Clark authored
[WHY] With some monitors when multi plane overlay is enabled the memory clock switching mechanism has to change and, due to an error in the initialization sequence, it may cause a black screen. [HOW] Change the firmware assisted memory clock switch initialization and tear-down sequence utilizing the prepare_bandwidth and optimize_bandwidth contexts. Reviewed-by:
Felipe Clark <feclark@amd.com> Tested-by:
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- 14 Dec, 2021 1 commit
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Martin Leung authored
why: Need interface to lower clocks when in dc (power save) mode. Must be able to work with p_state unsupported cases Can cause flicker when OS notifies us of dc state change how: added dal3 interface for KMD added pathway to query smu for this softmax added blank before clock change to override underflow added logic to change clk based on pstatesupport and softmax added logic in prepare/optimize_bw to conform while changing clocks Reviewed-by:
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- 13 Dec, 2021 1 commit
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Isabella Basso authored
This fixes warnings caused by global functions lacking prototypes:, such as: warning: no previous prototype for 'dcn303_hw_sequencer_construct' [-Wmissing-prototypes] 12 | void dcn303_hw_sequencer_construct(struct dc *dc) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... warning: no previous prototype for ‘amdgpu_has_atpx’ [-Wmissing-prototypes] 76 | bool amdgpu_has_atpx(void) { | ^~~~~~~~~~~~~~~ Reviewed-by:Isabella Basso <isabbasso@riseup.net> Signed-off-by:
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- 14 Sep, 2021 1 commit
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Josip Pavic authored
[Why] When ODM is enabled, ABM is blocked on dcn31 but unblocked on dcn30. Since the dcn31 firmware is now able to handle ABM interop with ODM, it is no longer necessary to block ABM when ODM is enabled. Since the dcn30 firmware does not handle ABM interop with ODM, leaving that combination unblocked can lead to one side of the screen appearing brighter than the other. [How] When ODM is enabled, unblock abm on dcn31 and block it on dcn30 Reviewed-by:
Mikita Lipski <mikita.lipski@amd.com> Signed-off-by:
Josip Pavic <Josip.Pavic@amd.com> Tested-by:
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- 08 Jun, 2021 1 commit
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Wyatt Wood authored
[Why + How] Visual confirm has no asic-specific logic, so we can refactor and unify these functions that are currently spread out across multiple dcn files. Add a new hw sequencer interface update_visual_confirm_color, and a new mpc function pointer set_bg_color. This will allow visual confirm to updated independently of MPCC blending updates. v2: squash in DCN3.1 fixes Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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- 27 May, 2021 1 commit
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Qingqing Zhuo authored
This reverts commit 3ca40237. Recent visual confirm changes are regressing the driver, causing a black screen on boot in some green sardine configs, or visual confirm is not updated at all. Signed-off-by:
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- 20 May, 2021 1 commit
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Wyatt Wood authored
[Why] Visual confirm will indicate if driver is programming the surface address. Refactor is required because much of the visual confirm logic is buried deep in the mpcc files. In addition, visual confirm is not updated during fast updates. [How] In order to have visual confirm for driver flips, visual confirm needs to be updated on every frame, including fast updates. Add a new hw sequencer interface update_visual_confirm_color, and a new mpc function pointer set_bg_color. v2: drop unused variable (Alex) Signed-off-by:
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- 09 Apr, 2021 1 commit
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Victor Lu authored
[why] Currently to view the DCC_EN bit the entire DTN log must be dumped. A compact method to view the DCC_EN bit is desirable. [how] Introduce new debugfs interface that only dumps the DCC_EN bit. Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en Signed-off-by:
Victor Lu <victorchengchi.lu@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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- 18 Feb, 2021 1 commit
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Aurabindo Pillai authored
New proposed sequence for HUBP blanking causes regressions where the hardware would fail to enter blank which triggers an assert in the new sequence. This change brings back the old sequence. Fixes: 985faf2c ("drm/amd/display: New sequence for HUBP blank") Signed-off-by:
Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Reviewed-by:
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- 14 Jan, 2021 2 commits
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Wesley Chalmers authored
[WHY] DCN30 has a bug where blanking HUBP blocks pstate allow unless HUBP_DISABLE is toggled afterwards. [HOW] Create a HW sequence for blanking HUBP. 1. Wait for enter VBLANK 2. Set HUBP_BLANK 3. Make sure HUBP_IN_BLANK = 1 4. Toggle HUBP_DISABLE on and off to perform soft reset All existing calls to hubp->funcs->set_blank should be replaced with this new sequence. In wait_for_mpcc_disconnect, only blank the pipe being disconnected, and leave all other pipes unmodified. Tested-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
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Jun Lei authored
[why] When OS reboots, and panel is turned off, T12 may not be maintained. T12 is defined as the interval between VDDC off (occurs at shutdown) and the next VDDC on (occurs when eDP is POST-ed) [how] DC already tracks panel power off time. Add a DC interface which DM can call during shutdown. Ideally this should be as late as possible during the shutdown sequence so the extra delay is minimal. Tested-by:
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- 05 Jan, 2021 1 commit
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Joshua Aberback authored
[How] - use dc interface instead of hwss interface in cursor functions, to keep dc->idle_optimizations_allowed updated - add dc interface to check if idle optimizations might apply to a plane Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Acked-by:
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- 02 Nov, 2020 1 commit
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Joshua Aberback authored
[Why] Prior commit "Blank HUBP during pixel data blank for DCN30" missed the call to set_disp_pattern_generator from set_crtc_test_pattern, which re-exposed the issue for which we initially blocked active-only p-state switching. [How] - remove dcn30_blank_pixel_data, set dcn30 back to dcn20 version - new hwss funciton set_disp_pattern_generator - dcn20 version just calls opp_set_disp_pattern_generator - dcn30 version implements the HUBP blank Signed-off-by:
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