- 08 Jul, 2020 14 commits
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Wesley Chalmers authored
[WHY] We want to be able to see SMU messages sent and their responses Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
Joshua Aberback <Joshua.Aberback@amd.com> Acked-by:
Eryk Brol <eryk.brol@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Joshua Aberback authored
[Why] Currently we don't explicitly send a request for a minimum PHYCLK, and we hope that the dependencies other clocks have will raise PHYCLK when needed. [How] - new clk_mgr function to keep track of PHYCLK requirements - request maximum requirement across all links - remove PHYCLK from clock state comparator, as it doesn't come from DML Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Anthony Koo authored
[Header Changes] - Drop unused firmware SCRATCH bits from interface Signed-off-by:
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Roman Li authored
[Why] VSC infoframe is needed for PSR. Previously only DMCU controller supported PSR. Now DMUB also implements PSR. [How] Remove VSC infoframe dependency on DMCU. Signed-off-by:
Roman Li <roman.li@amd.com> Reviewed-by:
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Jaehyun Chung authored
[Why] Current DAL behaviour is to not send VSIF if mode does not support VRR (ie. FS range is < 10Hz). However, we should still set FS Native Color Active bit in some unsupported mode cases. [How] Remove check for if VRR is supported before building infopacket. Signed-off-by:
Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by:
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Igor Kravchenko authored
[Why] Driver re-initialize registers already set in FW [How] Transfer init to FW Signed-off-by:
Igor Kravchenko <Igor.Kravchenko@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Print scaling parameters as they are calculated in diags. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Likun Gao authored
MMHUB powergating should be disabled on navi12 and enabled on sienna cichlid. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Likun Gao authored
Use RREG32_KIQ to read gfx register when try to get gfx/sdma clockgating state instead of RREG32, as it will result to system hard hang when GPU is enter into GFXOFF state. Signed-off-by:
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John Clements authored
add support for loading ucode with ta_firmware_header_v2_0 Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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John Clements authored
added definition for ta_firmware_header_v2_0 Reviewed-by:
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Huang Rui authored
TMR is required to be destoried with GFX_CMD_ID_DESTROY_TMR while the system goes to suspend. Otherwise, PSP may return the failure state (0xFFFF007) on Gfx-2-PSP command GFX_CMD_ID_SETUP_TMR after do multiple times suspend/resume. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Huang Rui authored
Unload ASD function in suspend phase. Signed-off-by:
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- 02 Jul, 2020 26 commits
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Colin Ian King authored
The variable result is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Alex Deucher authored
Large clock values may overflow and show up as negative. Reported by prOMiNd on IRC. Acked-by:
Nirmoy Das <nirmoy.das@amd.com> Signed-off-by:
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Alex Deucher authored
Add support for integrated_system_info table v12. Use the actual v12 structure. Acked-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
Used for renoir. Acked-by:
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Alex Deucher authored
Renoir uses integrated_system_info table v12. The table has the same layout as v11 with respect to this data. Just reuse the existing code for v12 for stable. Fixes incorrectly reported vram info in the driver output. Acked-by:
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Evan Quan authored
Fix the compile error below: drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c: In function 'smu_v11_0_init_microcode': >> arch/arc/include/asm/bug.h:22:2: error: implicit declaration of function 'pr_warn'; did you mean 'pci_warn'? [-Werror=implicit-function-declaration] 22 | pr_warn("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \ | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:176:3: note: in expansion of macro 'BUG' 176 | BUG(); Reported-by:kernel test robot <lkp@intel.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Changes that are fast don't require updating DLG parameters making this call unnecessary. Considering this is an expensive call it should not be done on every flip. DML touches clocks, p-state support, DLG params and a few other DC internal flags and these aren't expected during fast. A hang has been reported with this change when called on every flip which suggests that modifying these fields is not recommended behavior on fast updates. [How] Guard the validation to only happen if update type isn't FAST. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1191 Fixes: a24eaa5c ("drm/amd/display: Revalidate bandwidth before commiting DC updates") Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
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Pierre-Loup A. Griffais authored
It's otherwise properly supported, just needs exposing to userspace. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Pierre-Loup A. Griffais <pgriffais@valvesoftware.com> Signed-off-by:
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Joseph Greathouse authored
Add support for GWS in Arcturus, which needs MEC2 firmware #48 or above. Fix the MEC2 version check for Vega 10 GWS support, since Vega 10 firmware adds 0x8000 to the actual firmware revision. We were previously declaring support where it did not exist. Signed-off-by:
Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by:
Kent Russell <kent.russell@amd.com> Signed-off-by:
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Hawking Zhang authored
This reverts commit 2eee0229. Fallback to a stable base until we have a correct new one Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Monk Liu authored
issue: originally we kickoff IB test asynchronously with driver's init, thus the IB test may still running when the driver loading done (modprobe amdgpu done). if we shutdown VM immediately after amdgpu driver loaded then GPU may hang because the IB test is still running fix: flush the delayed_init routine at the bottom of device_init to avoid driver loading done prior to the IB test completes Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Acked-by:
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Joseph Greathouse authored
Update PROCESS_QUANTUM, the time the hardware scheduler allows processes to run before switching to other processes when it becomes over-subscribed. Increase this to 10ms, to allow processes to better amortize their task switch times. Update HQD Quantum, the amount of time that an active queue stays attached to the CP before we forcibly switch it for another active queue for fairness. Setting these so that HQD < PROCESS makes it easier to ensure that we get fairness when we have multiple active queues on the device. Otherwise we may start process-swapping before we get to all the queues in a CP. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Dmytro Laktyushkin authored
In case of certain display configurations we want to allow max detile buffer utilization by using 4 to 1 mpc combine Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Jing Zhou authored
[Why] Register key for AE or QA do regression test. New edid status for check. [How] Add register key edid_read_retry_times. Add new edid status EDID_FALL_BACK. Signed-off-by:
Jing Zhou <Jing.Zhou@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Anthony Koo authored
[Header Changes] - Add command for notification of active streams to DMUB Signed-off-by:
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Jaehyun Chung authored
[Why] In cases where refresh range is slightly below 10, FreeSync is not active or supported. Need to round values before checking refresh range in order to have FreeSync supported in these cases. [How] Remove redundant values and round values before checking valid refresh range. Signed-off-by:
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Anthony Koo authored
Signed-off-by:
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jinlong zhang authored
[Why] For special DP convert VGA dongle, core_link_read_dpcd for DP_DOWNSTREAM_PORT_0 always return fail, then dongle_type will be set to DISPLAY_DONGLE_NONE, which will cause desktop resolution abnormal. [How] If dpcd for DP_DOWNSTREAM_PORT_0 read fail, skip set dongle_type = DISPLAY_DONGLE_NONE. Signed-off-by:
jinlong zhang <jinlong.zhang@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Yongqiang Sun authored
[Why] SMU may return error code to driver, but driver only check if response is OK. [How] Check SMU response instead of reg_wait, assert in case of reponse isn't OK. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Anthony Koo authored
Signed-off-by:
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Joshua Aberback authored
[Why] We want to keep the same buffer allocated for use during multiple hardware initializations. [How] - allocate gpu memory buffer on clock manager construct - free gpu memory buffer on clock manager destruct Signed-off-by:
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Wyatt Wood authored
[Why] Debug flags are not set by default. [How] Set debug flags to 0 Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Wenhui Sheng authored
The legacy way to initialize discovery_tmr_size is using DISCOVERY_TMR_SIZE, while after we reduce DISCOVERY_TMR_SIZE from 64KB to 4KB, variable discovery_tmr_size is also reduced to 4KB, this is not correct, it still should be 64KB, discovery_tmr_size will be used to calculate ip_discovery reserved mem's start address and size. Using DISCOVERY_TMR_OFFSET to init discovery_tmr_size instead. Signed-off-by:
Wenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by:
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Evan Quan authored
To follow conventional style. And this unnecessary "@" confuses our userspace tool. Signed-off-by:
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Likun Gao authored
Update sienna_cichlid driver if header file to match pptable changes. Signed-off-by:
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