- 14 Jun, 2022 40 commits
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes: e4c5c4df ("iio: adc: new driver to support Linear technology's ltc2496") Signed-off-by:
Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by:
Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-22-jic23@kernel.org
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 72aa29ce ("iio: adc: hi8435: Holt HI-8435 threshold detector") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Note the fixes tag predates some changes to this line of code so automated application of this fix may fail. Fixes: 7f40e061 ("iio:adc:ad7949: Add AD7949 ADC driver family") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Note that some other fixes have applied to this line of code that may complicate automated backporting. Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes tag is clearly not where this was introduced but it is very unlikely anyone will back port it past that point. Fixes: 65dd3d3d ("staging:iio:ad7887: Squash everything into one file") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to reflect that separate cachelines 'may' be required. Fixes: a5f8c7da ("iio: adc: Add AD7768-1 ADC basic support") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to reflect the fact DMA safety 'may' require separate cachelines. Fixes: aa16c6bd ("iio:adc: Add support for AD7766/AD7767") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_ALIGN definition. Update the comment to reflect the fact DMA safety 'may' require separate cachelines. Fixes: 7989b4bb ("iio: adc: ad7616: Add support for AD7616 ADC") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to reflect that DMA safety 'may' require separate cachelines. Fixes tag is unlikely to be the actual introdution of the problem but is far enough back to cover any likely backporting. Fixes: 7a28fe3c ("staging:iio:ad7476: Squash driver into a single file.") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: be7fd3b8 ("iio:adc:ad7298 make the tx and rx buffers __be16") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 506d2e31 ("iio: adc: Add driver support for AD7292") Signed-off-by:
Marcelo Schmitt <marcelo.schmitt1@gmail.com> Acked-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 003f1d48 ("staging:iio:adc:ad7280a: Split buff[2] into tx and rx parts") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to reflect that DMA safety 'may' require separate cachelines. Fixes: 54e018da ("iio:ad7266: Mark transfer buffer as __be16") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is insufficient guarantee for non-coherent DMA. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 9cc9806e ("iio: accel: Add driver for Murata SCA3300 accelerometer") Signed-off-by:
Tomas Melin <tomas.melin@vaisala.com> Acked-by:
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Jonathan Cameron authored
____cacheline_aligned is insufficient guarantee for non-coherent DMA. Switch to the updated IIO_DMA_MINALIGN definition. The second alignment marking is left in place to avoid doing more than the simple fix in this patch. Fixes: ced5c03d ("staging:iio:accel:sca3000 merge files into one.") Fixes: 152a6a88 ("staging:iio:accel:sca3000 move to hybrid hard / soft buffer design.") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is insufficient guarantee for non-coherent DMA. Switch to the updated IIO_DMA_MINALIGN definition. Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is insufficient guarantee for non-coherent DMA. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: bf2a5600 ("iio: accel: Add support for Bosch BMA220") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is insufficient guarantee for non-coherent DMA. Switch to the updated IIO_DMA_MINALIGN definition. Update comment to reflect that DMA safety may require separate cachelines. Fixes: cbab791c ("iio: accel: add ADXL367 driver") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is insufficient guarantee for non-coherent DMA. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 327a0eaf ("iio: accel: adxl355: Add triggered buffer support") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is insufficient guarantee for non-coherent DMA. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 636d4463 ("iio: accel: Add driver support for ADXL313") Signed-off-by:
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Jonathan Cameron authored
Discussion of the series: https://lore.kernel.org/all/20220405135758.774016-1-catalin.marinas@arm.com/ mm, arm64: Reduce ARCH_KMALLOC_MINALIGN brought to my attention that our current IIO usage of L1CACHE_ALIGN is insufficient as their are Arm platforms out their with non coherent DMA and larger cache lines at at higher levels of their cache hierarchy. Rename the define to make it's purpose more explicit. It will be used much more widely going forwards (to replace incorrect ____cacheline_aligned markings. Note this patch will greatly reduce the padding on some architectures that have smaller requirements for DMA safe buffers. The history of changing values of ARCH_KMALLOC_MINALIGN via ARCH_DMA_MINALIGN on arm64 is rather complex. I'm not tagging this as fixing a particular patch from that route as it's not clear what to tag. Most recently a change to bring them back inline was reverted because of some Qualcomm Kryo cores with an L2 cache with 128-byte lines sitting above the point of coherency. c1132702 Revert "arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)" That reverts: 65688d2a arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES) which refers to the change originally being motivated by Thunder x1 performance rather than correctness. Fixes: 6f7c8ee5 ("staging:iio: Add ability to allocate private data space to iio_allocate_device") Signed-off-by:
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Stephen Boyd authored
Based on device tree setting, set the CS idle mode. Reviewed-by:
Gwendal Grignou <gwendal@chromium.org> Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20220503193937.3794477-3-swboyd@chromium.orgSigned-off-by:
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Stephen Boyd authored
We need to configure the sleep and idle mode of the CS pins for this device. Add a DT property to do this so pins are in a proper state during sleep (either hi-z, grounded, or pulled up to vdd). Reviewed-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220503193937.3794477-2-swboyd@chromium.orgSigned-off-by:
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Gwendal Grignou authored
Add ability to set the precharge internal resistance from the device tree. Signed-off-by:
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Gwendal Grignou authored
Allow configure the resistance used during precharge. Signed-off-by:
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Gwendal Grignou authored
Based on device tree setting, set the internal analog gain. Signed-off-by:
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Gwendal Grignou authored
Allow setting the configure the input analog gain. Signed-off-by:
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Gwendal Grignou authored
Based on device tree setting, set the internal compensation resistor. Signed-off-by:
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Gwendal Grignou authored
Allow setting the internal resistor used for compensation. Signed-off-by:
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Gwendal Grignou authored
Add ability to set the precharge internal resistance from the device tree. Signed-off-by:
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Gwendal Grignou authored
Allow configure the resistance used during precharge. Signed-off-by:
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Gwendal Grignou authored
Field for PROX_CTRL4 should contain PROX_CTRL4. Fixes: 4c18a890 ("iio:proximity:sx9324: Add SX9324 support") Signed-off-by:
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Jonathan Cameron authored
Using this approach as opposed to CONFIG_PM guards allows the compiler to remove the unused code instead of doing it manually. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220220175149.503495-3-jic23@kernel.org
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Jonathan Cameron authored
This driver is built as a single module. There is an note in the makefile about SPI support being a reason to split the build in future. That support has never arrived so drop these symbol exports. Signed-off-by:
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Jonathan Cameron authored
Avoid unnecessary pollution of the global symbol namespace by moving library functions in to a specific namespace and import that into the drivers that make use of the functions. For more info: https://lwn.net/Articles/760045/Signed-off-by:
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Jonathan Cameron authored
This function was introduced with the ability to pick a clock. There are no upstream users so presumably it isn't as obviously useful as it seemed at the time. Hence drop it. Signed-off-by:
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Cosmin Tanislav authored
The starting bit is always zero, it doesn't make much sense to use for_each_set_bit_from. Replace it with for_each_set_bit which doesn't start from a particular bit. Signed-off-by:
Cosmin Tanislav <cosmin.tanislav@analog.com> Reviewed-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20220111074703.3677392-3-cosmin.tanislav@analog.comSigned-off-by:
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Xiang wangx authored
Delete the redundant word 'via'. Signed-off-by:
Xiang wangx <wangxiang@cdjrlc.com> Link: https://lore.kernel.org/r/20220604040541.8470-1-wangxiang@cdjrlc.comSigned-off-by:
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LI Qingwu authored
Different from SCA3300, SCL3300 can output inclination angles. Angles are formed from acceleration with following equations: ANG_X = atan2(accx , sqrt(pow(accy , 2) + pow(accz , 2))) ANG_Y = atan2(accy , sqrt(pow(accx , 2) + pow(accz , 2))) ANG_Z = atan2(accz , sqrt(pow(accx , 2) + pow(accy , 2))) The commit adds the output of the raw value, scale and scale_available of angles. New interfaces: in_incli_scale in_incli_scale_available in_incli_x_raw in_incli_y_raw in_incli_z_raw Data converted by application of scale to degrees. Signed-off-by:
LI Qingwu <Qing-wu.Li@leica-geosystems.com.cn> Reviewed-by:
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LI Qingwu authored
Add support for Murata SCL3300, a 3-axis MEMS accelerometer. Same as SCA3300, it has the accelerometer and temperature output. Datasheet: www.murata.com/en-us/products/sensor/inclinometer/overview/lineup/scl3300 Signed-off-by:
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