- 20 Feb, 2013 1 commit
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Arnd Bergmann authored
This reverts commit f9965aa2. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 14 Feb, 2013 13 commits
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Padmavathi Venna authored
This patch adds #dma-cells property to PL330 DMA controller nodes for supporting generic dma dt bindings on samsung exynos5250 platform. Signed-off-by:
Padmavathi Venna <padma.v@samsung.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Padmavathi Venna authored
This patch registers the pl330 dma controller driver with the generic device tree dma helper functions. Signed-off-by:
Padmavathi Venna <padma.v@samsung.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Padmavathi Venna authored
Add xlate to translate the device-tree binding information into the appropriate format. The filter function requires the dma controller device and dma channel number as filter_params. Signed-off-by:
Padmavathi Venna <padma.v@samsung.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Padmavathi Venna authored
This patch adds a new pl330_dt_filter for DT case to filter the required channel based on the new filter params and modifies the old filter only for non-DT case as suggested by Arnd Bergmann. Signed-off-by:
Padmavathi Venna <padma.v@samsung.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Andy Shevchenko authored
There is no need to assign 0 to residue, because dma_cookie_status() does this for us. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Acked-by:
Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Andy Shevchenko authored
Accordingly to commentary in the platform_device_register_full the memory allocated for dma_mask will not going to be freed. That's why is better to assign dma_mask afterwards. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Andy Shevchenko authored
When status is DMA_SUCCESS the residue should be zero. Otherwise it's a bug. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Andy Shevchenko authored
In case the len is 0 we must return without trying to unlock the lock that was not locked. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Andy Shevchenko authored
dmaengine_device_control returns -ENOSYS in case the dma driver doesn't have such functionality. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Andy Shevchenko authored
It's possible to have an inconsistency in the list due to unprotected operation on it. The patch adds a proper locking on the list operation. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Rob Herring <rob.herring@calxeda.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Fabio Baltieri authored
Fix dma_tc_handle() to call d40_desc_remove() and d40_desc_done() only for non-cyclic transfers, as this was breaking ux500_pcm since introduced in: d49278e3 dmaengine: dma40: Add support to split up large elements Reported-by:
Shreshtha Kumar Sahu <shreshthakumar.sahu@stericsson.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Fabio Baltieri <fabio.baltieri@linaro.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Cong Ding authored
The memory allocated to ofdma might be a leakage when error occurs. Signed-off-by:
Cong Ding <dinggnu@gmail.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Andy Shevchenko authored
In some cases we got the device without dma_mask configured. We have to apply the default value to avoid crashes during memory mapping. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 13 Feb, 2013 2 commits
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Fengguang Wu authored
>> drivers/dma/ioat/dma_v3.c:371:6: sparse: symbol 'ioat3_timer_event' was not declared. Reported-by:
Fengguang Wu <fengguang.wu@intel.com> Signed-off-by:
Fengguang Wu <fengguang.wu@intel.com> Acked-by:
Dave Jiang <dave.jiang@intel.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Vinod Koul authored
as requested by Rob Suggested-by:
Rob Herring <rob.herring@calxeda.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 12 Feb, 2013 2 commits
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Dave Jiang authored
There is a race that can hit during __cleanup() when the ioat->head pointer is incremented during descriptor submission. The __cleanup() can clear the PENDING flag when it does not see any active descriptors. This causes new submitted descriptors to be ignored because the COMPLETION_PENDING flag is cleared. This was introduced when code was adapted from ioatdma v1 to ioatdma v2. For v2 and v3, IOAT_COMPLETION_PENDING flag will be abandoned and a new flag IOAT_CHAN_ACTIVE will be utilized. This flag will also be protected under the prep_lock when being modified in order to avoid the race. Signed-off-by:
Dave Jiang <dave.jiang@intel.com> Reviewed-by:
Dan Williams <djbw@fb.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Mika Westerberg authored
Intel Lynxpoint PCH Low Power Subsystem has DMA controller to support general purpose serial buses like SPI, I2C, and HSUART. This controller is enumerated from ACPI namespace with ACPI ID INTL9C60. Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 28 Jan, 2013 7 commits
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Andy Shevchenko authored
Currently the driver returns full length of the active descriptor which is wrong. We have to go throught the active descriptor and substract the length of each sent children in the chain from the total length along with the actual data in the DMA channel registers. The cyclic case is not handled by this patch due to len field in the descriptor structure is left untouched by the original code. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Andy Shevchenko authored
It will be useful to have the length of the transfer in the descriptor. The cyclic transfer functions remained untouched. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Andy Shevchenko authored
By this new field we distinguish a total length of the chain and the individual length of each descriptor in the chain. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Andy Shevchenko authored
The soft LLP mode is working for active descriptor only. So, we do not need to have a copy of its pointer. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Andy Shevchenko authored
It's usefull to have the values of the DW_PARAMS and DWC_PARAMS printed when debug mode is enabled. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Barry Song authored
Just like Russell pointed out in "DMAEngine: sirf: add DMA pause/resume support" at http://www.spinics.net/lists/arm-kernel/msg212496.html here I find sirfsoc_dma_terminate_all() has same problem, so move the locking to the front of registers access. Signed-off-by:
Barry Song <Baohua.Song@csr.com> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Barry Song authored
pause/resume are important for users like ALSA sound drivers, this patches make the sirf prima2/marco support DMA commands DMA_PAUSE and DMA_RESUME. Signed-off-by:
Barry Song <Baohua.Song@csr.com> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 21 Jan, 2013 4 commits
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Vinod Koul authored
Pull ste_dma40 fixes from Fabio Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Andy Shevchenko authored
The proper place for the main logic of the soft LLP mode is dwc_scan_descriptors. It prevents to get the transfer unexpectedly aborted in case the user calls dwc_tx_status. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Andy Shevchenko authored
The driver assumes that hardware has two AHB masters which might not be always true. In such cases we must not exceed number of the AHB masters present in the hardware. In the proposed scheme in this patch, we would choose the master with highest possible number whenever we exceed max AHB masters. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Andy Shevchenko authored
Currently descriptors are allocated from normal cacheable memory and that slows down filling the descriptors, as we need to call cache_coherency routines afterwards. It would be better to allocate memory for these descriptors from DMA_COHERENT memory. This would make code much cleaner too. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 20 Jan, 2013 3 commits
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Cong Ding authored
the variable chan is dereferenced in line 635, so it is no reason to check null again in line 641. Signed-off-by:
Cong Ding <dinggnu@gmail.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Cong Ding authored
the pointer cfg is dereferenced in line 594, so it's no reason to check null again in line 620. Signed-off-by:
Cong Ding <dinggnu@gmail.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Matt Porter authored
The edma_slave_config() implementation depends on the direction field such that it will not properly configure a slave channel when called without direction set. This fixes the implementation so that the slave config is copied as is and prep_slave_sg() handles the direction dependent handling. spi-omap2-mcspi and omap_hsmmc both expose this bug as they configure the slave channel config from a common path with an unconfigured direction field. Signed-off-by:
Matt Porter <mporter@ti.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 14 Jan, 2013 8 commits
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Fabio Baltieri authored
Clock code was changed to use clk_prepare_enable in: b707c65 dma/ste_dma40: Fixup clock usage during probe but clk_disable on probe fail path was not updated. This patch fix this by using clk_disable_unprepare in place of clk_disable. Acked-by:
Ulf Hansson <ulf.hansson@linaro.org> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Vinod Koul <vinod.koul@intel.com> Signed-off-by:
Fabio Baltieri <fabio.baltieri@linaro.org>
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Fabio Baltieri authored
Some DMA channels may be used by other cores in the SoC. This patch modifies the dma interrupt handler to ignore interrupts from unknown channels. Cc: Rabin Vincent <rabin.vincent@stericsson.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Vinod Koul <vinod.koul@intel.com> Signed-off-by:
Fabio Baltieri <fabio.baltieri@linaro.org>
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Fabio Baltieri authored
This patch add support to manage LLI by SW for select phy channels. There is a HW issue in certain controllers due to which on certain occassions HW LLI cannot be used on some physical channels. To avoid the HW issue on a specific phy channel, the phy channel number can be added to the list of soft_lli_channels and there after all the transfers on that channel will use software LLI, for peripheral to memory transfers. SoftLLI introduces relink overhead, that could impact performace for certain use cases. This is based on a previous patch of Narayanan Gopalakrishnan. Cc: Shreshtha Kumar Sahu <shreshthakumar.sahu@stericsson.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Vinod Koul <vinod.koul@intel.com> Signed-off-by:
Fabio Baltieri <fabio.baltieri@linaro.org>
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Fabio Baltieri authored
Use internal variables to the cycles to improve code readability, no functional changes. Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Vinod Koul <vinod.koul@intel.com> Signed-off-by:
Fabio Baltieri <fabio.baltieri@linaro.org>
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Fabio Baltieri authored
This patch contains various non functional cosmetic fixes. Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Vinod Koul <vinod.koul@intel.com> Signed-off-by:
Fabio Baltieri <fabio.baltieri@linaro.org>
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Fabio Baltieri authored
Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Vinod Koul <vinod.koul@intel.com> Signed-off-by:
Fabio Baltieri <fabio.baltieri@linaro.org>
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Fabio Baltieri authored
This is to keep the active queue for only those transfers which are actually active in the hardware. Descriptors will be moved to the done queue after they are completed in the hardware (interrupt handler) but before all the cleanup work has been completed (tasklet). Mostly based on a previous patch by Rabin Vincent. Cc: Rabin Vincent <rabin.vincent@stericsson.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Vinod Koul <vinod.koul@intel.com> Signed-off-by:
Fabio Baltieri <fabio.baltieri@linaro.org>
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Tong Liu authored
U8540 DMA controller is different from u9540 we need define new registers and use them to support handling more than 128 event lines. Signed-off-by:
Tong Liu <tong.liu@stericsson.com> Reviewed-by:
Per Forlin <per.forlin@stericsson.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Vinod Koul <vinod.koul@intel.com> Signed-off-by:
Fabio Baltieri <fabio.baltieri@linaro.org>
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