- 24 May, 2020 17 commits
-
-
Miquel Raynal authored
It seems that several hardware ECC engine use a swapped representation of bytes compared to software. This might having to do with how the ECC engine is wired to the NAND controller or the order the bits are passed to the hardware BCH logic. This means that when the software BCH engine is working in conjunction with data generated with hardware, sometimes we might need to swap the bits inside bytes, eg: 0x0A = b0000_1010 -> b0101_0000 = 0x50 Make it possible by adding a boolean to the BCH initialization routine. Regarding the implementation itself, this is a rather simple approach that can probably be enhanced in the future by preparing the ->a_{mod,pow}_tab tables with the swapping in mind. Suggested-by:Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by:
-
Miquel Raynal authored
There are four exported functions, all suffixed by _bch, which is clearly not the norm. Let's rename them by prefixing them with bch_ instead. This is a mechanical change: init_bch -> bch_init free_bch -> bch_free encode_bch -> bch_encode decode_bch -> bch_decode Signed-off-by: -
Miquel Raynal authored
There are controllers not able to just read data cycles on the bus. There are controllers not able to do a change column. If we want to support both, we need to check which operation is supported first. This is the exact same mechanism that is in use for parameter page reads (ONFI/JEDEC) as the same problem occurs. Speed testing does not show any throughput penalty so we do not optimize more than that. However it is likely that, in the future, a more robust and exhaustive test will run at boot time to avoid re-checking what is supported and what is not at every call. Signed-off-by:
-
Boris Brezillon authored
The CM-X270 board has been removed, we can remove the custom NAND driver as well. Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by:
-
Boris Brezillon authored
Mimic what's done in nand_soft_waitrdy() and add one to the jiffies timeout so we don't end up waiting less than actually required. Reported-by:
Tudor Ambarus <tudor.ambarus@microchip.com> Fixes: b0e137ad ("mtd: rawnand: Provide helper for polling GPIO R/B pin") Cc: <stable@vger.kernel.org> Signed-off-by:
-
Boris Brezillon authored
Now that exec_op() is implemented we can get rid of the legacy interface implementation. Signed-off-by:
Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by:
-
Boris Brezillon authored
Implement exec_op() so we can later get rid of the legacy interface implementation. Signed-off-by:
-
Boris Brezillon authored
We can use info->current_cs directly instead of doing this weird IO_ADDR_{R,W} re-assignment dance. Signed-off-by: -
Boris Brezillon authored
Let's not rely on the dummy_controller embedded in nand_chip.legacy and explicitly inherit from nand_controller instead. Signed-off-by:
-
Álvaro Fernández Rojas authored
The current code checks that the whole OOB area is erased. This is a problem when JFFS2 cleanmarkers are added to the OOB, since it will fail due to the usable OOB bytes not being 0xff. Correct this by only checking that data and ECC bytes aren't 0xff. Fixes: 02b88eea ("mtd: brcmnand: Add check for erased page bitflips") Signed-off-by:
Álvaro Fernández Rojas <noltari@gmail.com> Signed-off-by:
-
Álvaro Fernández Rojas authored
The current code generates 8 oob sections: S1 1-5 ECC 6-8 S2 9-15 S3 16-21 ECC 22-24 S4 25-31 S5 32-37 ECC 38-40 S6 41-47 S7 48-53 ECC 54-56 S8 57-63 Change it by merging continuous sections: S1 1-5 ECC 6-8 S2 9-21 ECC 22-24 S3 25-37 ECC 38-40 S4 41-53 ECC 54-56 S5 57-63 Signed-off-by:
-
Álvaro Fernández Rojas authored
First 2 bytes are used in large-page nand. Fixes: ef5eeea6 ("mtd: nand: brcm: switch to mtd_ooblayout_ops") Cc: stable@vger.kernel.org Signed-off-by:
-
Miquel Raynal authored
Xiaolei's address is bouncing, remove him from MAINTAINERS and mark the driver he was maintaining, Mediatek's, as orphaned. Signed-off-by:
-
Miquel Raynal authored
Piotr's address is bouncing, remove him from MAINTAINERS and mark the driver he was maintaining, Cadence's, as orphaned. Signed-off-by:
-
Boris Brezillon authored
Some controller using the instruction parse infrastructure might need to know which CS a specific sub-operation is targeting. Let's propagate this information. Signed-off-by:
-
Christophe Kerello authored
This patch removes custom macros and uses FIELD_PREP and FIELD_GET macros. Signed-off-by:
Christophe Kerello <christophe.kerello@st.com> Reviewed-by:
-
Christophe Kerello authored
This patch renames functions and local variables. This cleanup is done to get all functions starting by stm32_fmc2_nfc in the FMC2 raw NAND driver when all functions will start by stm32_fmc2_ebi in the FMC2 EBI driver. Signed-off-by:
-
- 11 May, 2020 23 commits
-
-
Christophe Kerello authored
This patch removes the constant FMC2_TIMEOUT_US. FMC2_TIMEOUT_MS will be used each time that we need to wait (except when the timeout value is set by the framework). It was seen, during stress tests with the sequencer in an overloaded system, that we could be close to 1 second, even if we never met this value. To be safe, FMC2_TIMEOUT_MS is set to 5 seconds. Signed-off-by:
-
Christophe Kerello authored
Remove inline comments that are useless since function label are self explanatory. Signed-off-by:
-
Christophe Kerello authored
This patch defers its probe when the expected reset control is not yet ready. This patch also handles properly all errors cases at probe time. Signed-off-by:
-
Boris Brezillon authored
Now that exec_op() has been implemented we can get rid of the legacy interface implementation. Signed-off-by:
-
Boris Brezillon authored
Implement exec_op() so we can later get rid of the legacy implementation. It's worth noting that the new implementation assert/deassert the CE pin on each operation, which might not be necessary. We also dropped the extra reset done at chip selection time on DOC2001plus. If it's needed we really should do something smarter, because having a reset everytime we access the chip is not that great perf-wise. Signed-off-by:
-
Boris Brezillon authored
Stop relying on the dummy controller object embedded in nand_chip.legacy and explicitly inherit from nand_controller. Signed-off-by:
-
Boris Brezillon authored
The logic can easily be merged in doc2000_readbuf(). Signed-off-by:
-
Boris Brezillon authored
Single byte accesses normally go through read_byte() but we are about to use this function in the exec_op() implementation and thus needs to prepare for single byte reads. Signed-off-by:
-
Boris Brezillon authored
We have a dummy block_bad() implementation returning 0. Let's set the NAND_NO_BBM_QUIRK flag and let the core take care of that. Signed-off-by:
-
Boris Brezillon authored
We have a dummy block_bad() implementation returning 0. Let's set the NAND_NO_BBM_QUIRK flag and let the core take care of that. Signed-off-by:
-
Boris Brezillon authored
Some controllers with embedded ECC engines override the BBM marker with data or ECC bytes, thus making bad block detection through bad block marker impossible. Let's flag those chips so the core knows it shouldn't check the BBM and consider all blocks good. This should allow us to get rid of two implementers of the legacy.block_bad() hook. Signed-off-by:
-
Miquel Raynal authored
Some controller drivers do not support executing regular nand_read/write_page_raw() helpers. For that, we created nand_monolithic_read/write_page_raw() alternatives. Let's now allow the driver to overload the ECC ->read/write_page_raw() hooks when these hooks are supported. Signed-off-by:
-
Miquel Raynal authored
Some controller drivers do not support executing regular nand_read/write_page_raw() helpers. For that, we created nand_monolithic_read/write_page_raw() alternatives. Let's now allow the driver to overload the ECC ->read/write_page_raw() hooks. Signed-off-by:
-
Miquel Raynal authored
The current nand_read/write_page_raw() helpers are already widely used but do not fit the purpose of "constrained" controllers which cannot, for instance, separate command/address cycles with data cycles. Workaround this issue by proposing alternative helpers that can be used by these controller drivers instead. Signed-off-by:
-
Miquel Raynal authored
We already know that there are controllers not able to read the three copies of the parameter page in one go. The workaround was to first request the controller to assert command and address cycles on the NAND bus to trigger a parameter page read, and then do a read operation for each page. But there are also controllers which are not able to split the parameter page read between the command/address cycles and the actual data operation. Let's use a regular PARAMETER PAGE READ operation for the first iteration and use eithe a CHANGE READ COLUMN or a simple DATA READ operation for the following copies, depending on what the controller supports. The default for non-exec-op compliant drivers remains unchanged: use a SIMPLE READ. Signed-off-by:
-
Miquel Raynal authored
We already know that there are controllers not able to read the three copies of the parameter page in one go. The workaround was to first request the controller to assert command and address cycles on the NAND bus to trigger a parameter page read, and then do a simple read operation for each page. But there are also controllers which are not able to split the parameter page read between the command/address cycles and the actual data operation. Let's use a regular PARAMETER PAGE READ operation for the first iteration and use either a CHANGE READ COLUMN or a simple DATA READ operation for the following copies, depending on what the controller supports. The default behavior for non-exec-op compliant drivers remains the same: DATA READ. Signed-off-by:
-
Miquel Raynal authored
This can be used to discriminate between two path in the parameter page detection: use data_in cycles (like before) if supported, use the CHANGE READ COLUMN command otherwise. Signed-off-by:
-
Miquel Raynal authored
Let's use a helper to clearly check if an operation is supported or not. Return -ENOTSUPP when ->exec_op() is not implemented as we cannot know. Signed-off-by:
-
Miquel Raynal authored
The logic in nand_do_read_ops() is to use a bufpoi variable, either set to the original buffer, or set to a bounce buffer which in the end happens to be chip->data_buf depending on the value of the use_bounce_buf boolean. This is not a reason to call chip->data_buf directly when we know that we are using the bounce buffer. Let's use bufpoi instead to be consistent. Signed-off-by:
-
Miquel Raynal authored
Both in nand_do_read_ops() and nand_do_write_ops() there is a boolean called use_bufpoi which is set to true in case of unaligned request or when there is a need for a DMA-able buffer. It basically means "use a bounce buffer". Depending on the value of use_bufpoi, the bufpoi variable is always used and will either point to the original buffer or to the nand_chip structure "internal data buffer" (this buffer is allocated with kmalloc() on purpose so that it will be DMA-compliant). In all cases bufpoi is used so the boolean name is misleading. Rename use_bufpoi to be use_bouce_buf to be more accurate. Signed-off-by:
-
Miquel Raynal authored
Clarify these comments which are not very accurate (even wrong in the read case). Signed-off-by:
-
Miquel Raynal authored
NAND controller drivers can set the NAND_USE_BOUNCE_BUFFER flag to a chip 'option' field. With this flag, the core is responsible of providing DMA-able buffers. The current behavior is to not force the use of a bounce buffer when the core thinks this is not needed. So in the end the name is a bit misleading, because in theory we will always have a DMA buffer but in practice it will not always be a bounce buffer. Rename this flag NAND_USES_DMA to be more accurate. Signed-off-by:
-
Miquel Raynal authored
These flags are in a strange order, reorder the list, add spaces when it is relevant, pack definitions that are related. There is no functional change. Signed-off-by:
-
