- 12 Dec, 2019 3 commits
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D32 is simple version of D71, the difference is: - Only has one pipeline - Drop the periph block and merge it to GCU v2: Rebase. v3: Isolate the block counting fix to a new patch Signed-off-by:
James Qian Wang (Arm Technology China) <james.qian.wang@arm.com> Reviewed-by:
Mihail Atanassov <mihail.atanassov@arm.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191210084828.19664-3-james.qian.wang@arm.com
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1. Drop komeda-CORE product id comparison and put it into the d71_identify 2. Update pipeline node DT-binding: (a). Skip the needless pipeline DT node. (b). Return fail if the essential pipeline DT node is missing. With these changes, for chips in same family no need to change the DT. v2: Rebase v3: Address Mihail's comments. Signed-off-by:
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Per HW, d71->num_blocks includes reserved blocks but no PERIPH block, correct the block counting accordingly. D71 happens to only have one reserved block and periph block, which hides this counting error. Signed-off-by:
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- 11 Dec, 2019 17 commits
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Thomas Zimmermann authored
The remaining code in udl_fb.c is unused. Remove the file entirely. Signed-off-by:
Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by:
Emil Velikov <emil.l.velikov@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191210084905.5570-10-tzimmermann@suse.de
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Thomas Zimmermann authored
The only caller of udl_handle_damage() in the plane-update function in udl_modeset.c. Move udl_handle_damage() there. v2: * remove udl_fb.c in a separate patch Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by:
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Thomas Zimmermann authored
The udl driver stores the currently active framebuffer to know from where to accept damage updates. With the conversion to plane-state damage handling, this is not necessary any longer. The currently active framebuffer and damaged area are always stored in the plane state. Signed-off-by:
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Thomas Zimmermann authored
The infrastruture for atomic modesetting allows us to use the generic code for dirty-FB and damage handling. Switch over udl and remove the driver's implementation. The simple-pipe's update function now picks up the primary plane's damage and updates a minimal region of the screen. Signed-off-by:
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Thomas Zimmermann authored
The current default color depth of 24 bpp is not even supported by the driver. Being the native format for communicating with the adapter, 16 bpp is the correct choice. Signed-off-by:
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Thomas Zimmermann authored
DPMS functionality is only used by the CRTC's enable and disable functions. Inline the code. The patch also adds symbolic constants for the blank register and constants; according to udlfb, which is a bit more detailed than DRM's udl. v3: * use symbolic constants for blank, according to udlfb driver Signed-off-by:
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Thomas Zimmermann authored
We can use the generic suspend/resume helpers for atomic modesetting. Switch udl over. Signed-off-by:
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Thomas Zimmermann authored
Udl has a single display pipeline with a primary plane; perfect for simple-pipe helpers. Convert it over. The old encoder and CRTC code becomes unused and obsolete. Exported formats for the primary plane are RGB565 and XRGB8888, with the latter being emulated. The 16-bit format is the default and what is used when communicating with the device. This patch enables atomic modesetting for udl devices. v3: * remove unused field crtc from struct udl_device * set crtc_state->no_vblank at beginning of enable() v2: * move suspend/resume changes into separate patch * remove non-atomic code Signed-off-by:
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Thomas Zimmermann authored
To mimic simple-pipe, we initialize the connector before the rest of the display pipeline. v2: * remove unnecessary calls to drm_connector_{register,unregister}() Signed-off-by: -
Thomas Anderson authored
CEA-861-G adds modes up to 219, so increase the size of the maps in preparation for adding the new modes to drm_edid.c. Signed-off-by:
Thomas Anderson <thomasanderson@google.com> Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191210221048.83628-1-thomasanderson@google.com
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Jani Nikula authored
Now that the fbops member of struct fb_info is const, we can start making the ops const as well. Cc: Miguel Ojeda Sandonis <miguel.ojeda.sandonis@gmail.com> Cc: Robin van der Gracht <robin@protonic.nl> Reviewed-by:
Miguel Ojeda <miguel.ojeda.sandonis@gmail.com> Acked-by:
Robin van der Gracht <robin@protonic.nl> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/31c18e3ce9d6962aabda4799b3051039ff591c92.1575390741.git.jani.nikula@intel.com
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John Stultz authored
Add very trivial allocation and import test for dma-heaps, utilizing the vgem driver as a test importer. A good chunk of this code taken from: tools/testing/selftests/android/ion/ionmap_test.c Originally by Laura Abbott <labbott@redhat.com> Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org> Cc: Sumit Semwal <sumit.semwal@linaro.org> Cc: Liam Mark <lmark@codeaurora.org> Cc: Pratik Patel <pratikp@codeaurora.org> Cc: Brian Starkey <Brian.Starkey@arm.com> Cc: Vincent Donnefort <Vincent.Donnefort@arm.com> Cc: Sudipto Paul <Sudipto.Paul@arm.com> Cc: Andrew F. Davis <afd@ti.com> Cc: Christoph Hellwig <hch@infradead.org> Cc: Chenbo Feng <fengc@google.com> Cc: Alistair Strachan <astrachan@google.com> Cc: Hridya Valsaraju <hridya@google.com> Cc: Sandeep Patil <sspatil@google.com> Cc: Hillf Danton <hdanton@sina.com> Cc: Dave Airlie <airlied@gmail.com> Cc: dri-devel@lists.freedesktop.org Reviewed-by:
Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by:
Brian Starkey <brian.starkey@arm.com> Acked-by:
Sandeep Patil <sspatil@android.com> Acked-by:
Laura Abbott <labbott@redhat.com> Tested-by:
Ayan Kumar Halder <ayan.halder@arm.com> Signed-off-by:
John Stultz <john.stultz@linaro.org> Signed-off-by:
Sumit Semwal <sumit.semwal@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20191203172641.66642-6-john.stultz@linaro.org
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John Stultz authored
This adds a CMA heap, which allows userspace to allocate a dma-buf of contiguous memory out of a CMA region. This code is an evolution of the Android ION implementation, so thanks to its original author and maintainters: Benjamin Gaignard, Laura Abbott, and others! NOTE: This patch only adds the default CMA heap. We will enable selectively adding other CMA memory regions to the dmabuf heaps interface with a later patch (which requires a dt binding) Cc: Laura Abbott <labbott@redhat.com> Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org> Cc: Sumit Semwal <sumit.semwal@linaro.org> Cc: Liam Mark <lmark@codeaurora.org> Cc: Pratik Patel <pratikp@codeaurora.org> Cc: Brian Starkey <Brian.Starkey@arm.com> Cc: Vincent Donnefort <Vincent.Donnefort@arm.com> Cc: Sudipto Paul <Sudipto.Paul@arm.com> Cc: Andrew F. Davis <afd@ti.com> Cc: Christoph Hellwig <hch@infradead.org> Cc: Chenbo Feng <fengc@google.com> Cc: Alistair Strachan <astrachan@google.com> Cc: Hridya Valsaraju <hridya@google.com> Cc: Sandeep Patil <sspatil@google.com> Cc: Hillf Danton <hdanton@sina.com> Cc: Dave Airlie <airlied@gmail.com> Cc: dri-devel@lists.freedesktop.org Reviewed-by:
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John Stultz authored
This patch adds system heap to the dma-buf heaps framework. This allows applications to get a page-allocator backed dma-buf for non-contiguous memory. This code is an evolution of the Android ION implementation, so thanks to its original authors and maintainters: Rebecca Schultz Zavin, Colin Cross, Laura Abbott, and others! Cc: Laura Abbott <labbott@redhat.com> Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org> Cc: Sumit Semwal <sumit.semwal@linaro.org> Cc: Liam Mark <lmark@codeaurora.org> Cc: Pratik Patel <pratikp@codeaurora.org> Cc: Brian Starkey <Brian.Starkey@arm.com> Cc: Vincent Donnefort <Vincent.Donnefort@arm.com> Cc: Sudipto Paul <Sudipto.Paul@arm.com> Cc: Andrew F. Davis <afd@ti.com> Cc: Christoph Hellwig <hch@infradead.org> Cc: Chenbo Feng <fengc@google.com> Cc: Alistair Strachan <astrachan@google.com> Cc: Hridya Valsaraju <hridya@google.com> Cc: Sandeep Patil <sspatil@google.com> Cc: Hillf Danton <hdanton@sina.com> Cc: Dave Airlie <airlied@gmail.com> Cc: dri-devel@lists.freedesktop.org Reviewed-by:
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John Stultz authored
Add generic helper dmabuf ops for dma heaps, so we can reduce the amount of duplicative code for the exported dmabufs. This code is an evolution of the Android ION implementation, so thanks to its original authors and maintainters: Rebecca Schultz Zavin, Colin Cross, Laura Abbott, and others! Cc: Laura Abbott <labbott@redhat.com> Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org> Cc: Sumit Semwal <sumit.semwal@linaro.org> Cc: Liam Mark <lmark@codeaurora.org> Cc: Pratik Patel <pratikp@codeaurora.org> Cc: Brian Starkey <Brian.Starkey@arm.com> Cc: Vincent Donnefort <Vincent.Donnefort@arm.com> Cc: Sudipto Paul <Sudipto.Paul@arm.com> Cc: Andrew F. Davis <afd@ti.com> Cc: Christoph Hellwig <hch@infradead.org> Cc: Chenbo Feng <fengc@google.com> Cc: Alistair Strachan <astrachan@google.com> Cc: Hridya Valsaraju <hridya@google.com> Cc: Sandeep Patil <sspatil@google.com> Cc: Hillf Danton <hdanton@sina.com> Cc: Dave Airlie <airlied@gmail.com> Cc: dri-devel@lists.freedesktop.org Reviewed-by:
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Andrew F. Davis authored
This framework allows a unified userspace interface for dma-buf exporters, allowing userland to allocate specific types of memory for use in dma-buf sharing. Each heap is given its own device node, which a user can allocate a dma-buf fd from using the DMA_HEAP_IOC_ALLOC. This code is an evoluiton of the Android ION implementation, and a big thanks is due to its authors/maintainers over time for their effort: Rebecca Schultz Zavin, Colin Cross, Benjamin Gaignard, Laura Abbott, and many other contributors! Cc: Laura Abbott <labbott@redhat.com> Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org> Cc: Sumit Semwal <sumit.semwal@linaro.org> Cc: Liam Mark <lmark@codeaurora.org> Cc: Pratik Patel <pratikp@codeaurora.org> Cc: Brian Starkey <Brian.Starkey@arm.com> Cc: Vincent Donnefort <Vincent.Donnefort@arm.com> Cc: Sudipto Paul <Sudipto.Paul@arm.com> Cc: Andrew F. Davis <afd@ti.com> Cc: Christoph Hellwig <hch@infradead.org> Cc: Chenbo Feng <fengc@google.com> Cc: Alistair Strachan <astrachan@google.com> Cc: Hridya Valsaraju <hridya@google.com> Cc: Sandeep Patil <sspatil@google.com> Cc: Hillf Danton <hdanton@sina.com> Cc: Dave Airlie <airlied@gmail.com> Cc: dri-devel@lists.freedesktop.org Reviewed-by:
Andrew F. Davis <afd@ti.com> Signed-off-by:
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Sam Ravnborg authored
Fix link failure for module builds of panels. The conditional compilation around drm_panel_of_backlight() was wrong for a module build. Fix it using IS_ENABLED(). Signed-off-by:
Sam Ravnborg <sam@ravnborg.org> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Fixes: 152dbdea ("drm/panel: add backlight support") Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Maxime Ripard <maxime.ripard@bootlin.com> Cc: Sean Paul <sean@poorly.run> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Maxime Ripard <mripard@kernel.org> Cc: dri-devel@lists.freedesktop.org Link: https://patchwork.freedesktop.org/patch/msgid/20191210194758.24087-1-sam@ravnborg.org
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- 10 Dec, 2019 20 commits
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Daniel Vetter authored
Kernel sphinx has learned how to do that in commit d74b0d31 Author: Jonathan Corbet <corbet@lwn.net> Date: Thu Apr 25 07:55:07 2019 -0600 Docs: An initial automarkup extension for sphinx Unfortunately it hasn't learned that yet for structures, so we're stuck with the :c:type: noise for now still. Reviewed-by:
Thierry Reding <treding@nvidia.com> Cc: Jonathan Corbet <corbet@lwn.net> Signed-off-by:
Daniel Vetter <daniel.vetter@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191204101933.861169-1-daniel.vetter@ffwll.ch
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Daniel Vetter authored
Both locking and especially sequencing of nonblocking commits have evolved a lot. The details are all there, but I noticed that the big picture and connections have fallen behind a bit. Apply polish. Motivated by some review discussions with Thierry. v2: Review from Thierry Reviewed-by:
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Mihail Atanassov authored
The function was unexported and was causing link failures for pl111 (and probably the other user tve200) in a module build. Fixes: d383fb5f ("drm: get drm_bridge_panel connector via helper") Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Linux Walleij <linux.walleij@linaro.org> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Thomas Zimmermann authored
Reading the primary plane's framebuffer from the CRTC's atomic_flush() function is fragile as the plane state or framebuffer can be NULL. Instead, we let the plane's atomic_check() store the framebuffer format in the CRTC state. The CRTC always receives the framebuffer format that is currently programmed, or NULL if no mode has been set yet. Signed-off-by:
Gerd Hoffmann <kraxel@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191202111557.15176-8-tzimmermann@suse.de
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Thomas Zimmermann authored
After looking up VBIOS mode information in CRTC's atomic_check(), we can reuse it in atomic_flush(). No need for a second look-up. Signed-off-by:
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Thomas Zimmermann authored
AST-specific CRTC state can be placed in the new struct ast_crtc_state. The atomic check functions of the CRTC and the primary plane will store the VBIOS mode info and the framebuffer format here. The CRTC will consume these during atomic_flush(). Signed-off-by:
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Thomas Zimmermann authored
Introducing atomic_check() for priamry and cursor plane. The functions validate the plane state and will later set format information for the CRTC's atomic_flush(). Signed-off-by:
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Thomas Zimmermann authored
In preparation of an update of the primary-plane code, this patch changes the arguments of several register-setting functions. No functional changes are made. The function ast_set_dac_reg() has no effect and therefore gets removed entirely. Signed-off-by:
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Thomas Zimmermann authored
Enabling and disabling the screen used to be done in the register initialization and the DPMS function. None of these places is related to the screen's output. Now the primary plane's update and disable functions handle screen display state. The primary plane can now be switched off without displaying garbage. Signed-off-by:
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Thomas Zimmermann authored
When enabling the CRTC after waking up from a power-saving mode, the primary plane's framebuffer might be NULL, which leads to a stack trace as shown below. [ 632.624608] BUG: kernel NULL pointer dereference, address: 0000000000000048 [ 632.624631] #PF: supervisor read access in kernel mode [ 632.624639] #PF: error_code(0x0000) - not-present page [ 632.624647] PGD 0 P4D 0 [ 632.624654] Oops: 0000 [#1] SMP PTI [ 632.624662] CPU: 0 PID: 2082 Comm: gnome-shell Tainted: G E 5.4.0-rc7-1-default+ #114 [ 632.624673] Hardware name: Sun Microsystems SUN FIRE X2270 M2/SUN FIRE X2270 M2, BIOS 2.05 07/01/2010 [ 632.624689] RIP: 0010:ast_crtc_helper_atomic_enable+0x7d/0x680 [ast] [ 632.624698] Code: 48 8b 80 e0 02 00 00 4c 8b 60 10 31 c0 f3 48 ab 48 8b 83 78 04 00 00 4c 89 ef 48 8d 70 18 e8 9a e9 55 ce 48 8b 83 78 04 00 00 <49> 8b 7c 24 48 4c 89 ea 4c 8d 44 24 28 48 8d 4c 24 20 48 8d 70 18 [ 632.624718] RSP: 0018:ffffbe9ec123fa40 EFLAGS: 00010246 [ 632.624726] RAX: ffff95a13cfd3400 RBX: ffff95a13cf32000 RCX: 0000000000000000 [ 632.624735] RDX: 0000000000000000 RSI: ffff95a13cfd34e8 RDI: ffffbe9ec123fb40 [ 632.624744] RBP: ffffbe9ec123fb80 R08: 0000000000000000 R09: 0000000000000003 [ 632.624753] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000 [ 632.624762] R13: ffffbe9ec123fa70 R14: ffff95a13beb7000 R15: ffff95a13cf32800 [ 632.624772] FS: 00007f6d2763e140(0000) GS:ffff95a134000000(0000) knlGS:0000000000000000 [ 632.624782] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 632.624790] CR2: 0000000000000048 CR3: 00000001192f8004 CR4: 00000000000206f0 [ 632.624800] Call Trace: [ 632.624811] ? __lock_acquire+0x409/0x7c0 [ 632.624830] drm_atomic_helper_commit_modeset_enables+0x1af/0x200 [ 632.624840] drm_atomic_helper_commit_tail+0x32/0x70 [ 632.624849] commit_tail+0xc7/0x110 [ 632.624857] drm_atomic_helper_commit+0x121/0x130 [ 632.624867] drm_atomic_connector_commit_dpms+0xd7/0x100 [ 632.624878] set_property_atomic+0xaf/0x110 [ 632.624890] drm_mode_obj_set_property_ioctl+0xbb/0x190 [ 632.624899] ? drm_mode_obj_find_prop_id+0x40/0x40 [ 632.624909] drm_ioctl_kernel+0x86/0xd0 [ 632.624918] drm_ioctl+0x1e4/0x36b [ 632.624925] ? drm_mode_obj_find_prop_id+0x40/0x40 [ 632.624939] do_vfs_ioctl+0x4bd/0x6e0 [ 632.624949] ksys_ioctl+0x5e/0x90 [ 632.624957] __x64_sys_ioctl+0x16/0x20 [ 632.624966] do_syscall_64+0x5a/0x220 [ 632.624976] entry_SYSCALL_64_after_hwframe+0x49/0xbe [ 632.624984] RIP: 0033:0x7f6d2b0de387 [ 632.624991] Code: 00 00 90 48 8b 05 f9 9a 0c 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d c9 9a 0c 00 f7 d8 64 89 01 48 [ 632.625011] RSP: 002b:00007fffb49def38 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 [ 632.625021] RAX: ffffffffffffffda RBX: 00007fffb49def70 RCX: 00007f6d2b0de387 [ 632.625030] RDX: 00007fffb49def70 RSI: 00000000c01864ba RDI: 0000000000000009 [ 632.625040] RBP: 00000000c01864ba R08: 0000000000000000 R09: 00000000c0c0c0c0 [ 632.625049] R10: 0000000000000030 R11: 0000000000000246 R12: 000055bc367eb920 [ 632.625058] R13: 0000000000000009 R14: 0000000000000002 R15: 0000000000000000 [ 632.625071] Modules linked in: ebtable_filter(E) ebtables(E) ip6table_filter(E) ip6_tables(E) iptable_filter(E) ip_tables(E) x_tables(E) af_packet(E) scsi_transport_iscsi(E) dmi_sysfs(E) msr(E) xfs(E) intel_powerclamp(E) coretemp(E) k) [ 632.625185] CR2: 0000000000000048 The STR is * start gdm and wait for it to switch off the display * wake up the display by pressing a key CRTC modesetting depends on the new state of the CRTC and the primary plane's framebuffer. The bugfix moves the modesetting code into the CRTC's atomic_flush() function, where it is protected from the plane's framebuffer being NULL. The CRTC's atomic-enable function, which is the modesetting's original location, still contains DPMS state handling. It's exactly the inverse of the atomic-disable function. v3: * protect modesetting from from fb == NULL v2: * do an atomic check for plane * reject invisible primary planes Signed-off-by:
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Neil Armstrong authored
Finally, setup the VIU registers and start the AFBC decoder to support displaying AFBC encoded buffers on Amlogic GXM and G12A SoCs. The RDMA is used here to reset and program the AFBC decoder unit on each vsync without involving the interrupt handler that can be masked for a long period of time, producing display glitches. The vsync irq must still be left enabled otherwise the RDMA modules isn't trigerred when the interrupt line is masked. Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Reviewed-by:
Kevin Hilman <khilman@baylibre.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-10-narmstrong@baylibre.com
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Neil Armstrong authored
When using an AFBC encoded frame, the AFBC Decoder must be reset, configured and enabled at each vsync IRQ. To leave time for that, use the maximum lines hold time to give time for AFBC setup and avoid visual glitches. Signed-off-by:
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Neil Armstrong authored
The Amlogic G12A AFBC Decoder pixel input need to be routed diferently than the Amlogic GXM AFBC decoder, this adds support for routing the VIU OSD1 pixel source to the AFBC "Mali Unpack" module. This "Mali Unpack" module is also configured with a static RGBA mapping for now until we support more pixel formats. Signed-off-by:
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Neil Armstrong authored
This adds all the OSD configuration plumbing to support the AFBC decoders path to display of the OSD1 plane. The Amlogic GXM and G12A AFBC decoders are integrated very differently. The Amlogic GXM has a direct output path to the OSD1 VIU pixel input, because the GXM AFBC decoder seem to be a custom IP developed by Amlogic. On the other side, the Amlogic G12A AFBC decoder seems to be an external IP that emit pixels on an AXI master hooked to a "Mali Unpack" block feeding the OSD1 VIU pixel input. This uses a weird "0x1000000" internal HW physical address on both sides to transfer the pixels. For Amlogic GXM, the supported pixel formats are the same as the normal linear OSD1 mode. On the other side, Amlogic added support for all AFBC v1.2 formats for the G12A AFBC integration. For simplicity, we stick to the already supported formats for now. Signed-off-by:
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Neil Armstrong authored
This adds the driver for the ARM Framebuffer Compression decoders found in the Amlogic GXM and G12A SoCs. The Amlogic GXM and G12A AFBC decoder are totally different, the GXM only handling only the AFBC v1.0 modes and the G12A decoder handling the AFBC v1.2 modes. The G12A AFBC decoder is an external IP integrated in the video pipeline, and the GXM AFBC decoder seems to the an Amlogic custom decoder more tighly integrated in the video pipeline. The GXM AFBC decoder can handle only one AFBC plane for 2 available OSD planes available in HW, and the G12A AFBC decoder can handle up to 4 AFBC planes for up to 3 OSD planes available in HW. The Amlogic GXM supports 16x16 SPARSE and 16x16 SPLIT AFBC buffers up to 4k. On the other side, for G12A SPLIT is mandatory in 16x16 block mode, but for 4k modes 32x8+SPLIT AFBC buffers is manadatory for performances reasons. The RDMA is used here to reset and program the AFBC decoder unit on each vsync without involving the interrupt handler that can be masked for a long period of time, producing display glitches. For this we use the meson_rdma_writel_sync() which adds the register write tuple (VPU register offset and register value) to the RDMA buffer and write the value to the HW. When enabled, the RDMA is enabled to rewrite the same sequence at the next VSYNC event, until a new buffer is committed to the OSD plane. Then the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder doesn't need a reset/reprogram at each vsync, but needs to keep the vsync interrupt enabled to trigger the RDMA module. Signed-off-by:
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Neil Armstrong authored
The VPU embeds a "Register DMA" that can write a sequence of registers on the VPU AHB bus, either manually or triggered by an internal IRQ event like VSYNC or a line input counter. The initial implementation handles a single channel (over 8), triggered by the VSYNC irq and does not handle the RDMA irq. The RDMA will be usefull to reset and program the AFBC decoder unit on each vsync without involving the interrupt handler that can be masked for a log period of time, producing display glitches. Signed-off-by:
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Neil Armstrong authored
Also store the framebuffer width in the private common struct to be used by the AFBC decoder module driver when committing the AFBC plane. Signed-off-by:
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Neil Armstrong authored
The Amlogic VPU embeds a "Register DMA" that can write a sequence of registers on the VPU AHB bus, either manually or triggered by an internal IRQ event like VSYNC or a line input counter. This adds the register defines. Signed-off-by:
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Neil Armstrong authored
Add the registers used to program the ARM Framebuffer Compression decoders used in the Amlogic GXM and G12A SoCs families. This also adds the routing and pipeline configuration bits and registers needed to enable AFBC support. Signed-off-by:
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Jani Nikula authored
Now that the fbops member of struct fb_info is const, we can start making the ops const as well. v2: fix typo (Christophe de Dinechin) Cc: Kirti Wankhede <kwankhede@nvidia.com> Cc: kvm@vger.kernel.org Reviewed-by:
Kirti Wankhede <kwankhede@nvidia.com> Signed-off-by:
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