- 28 Apr, 2020 20 commits
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Yongqiang Sun authored
[Why & How] Add panel cntl instance when calling set backlight. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
Tony Cheng <Tony.Cheng@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nicholas Kazlauskas authored
[Why] We read memory that we shouldn't be touching if the struct isn't a full union dmub_rb_cmd. [How] Fix up all the callers and functions that take in the dmub_cmd_header to use the dmub_rb_cmd instead. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
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Sung Lee authored
[WHY] The downspread percentage was copied over from a previous version of the display_mode_lib spreadsheet. This value has been updated, and the previous value is too high to allow for such modes as 4K120hz. The new value is sufficient for such modes. [HOW] Update the value in dcn21_resource to match the spreadsheet. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] Fixes the following scenario: - Flip has been prepared sometime during the frame, update pending - Cursor update happens right when VUPDATE would happen - OPTC lock acquired, VUPDATE is blocked until next frame - Flip is delayed potentially infinitely With the igt@kms_cursor_legacy cursor-vs-flip-legacy test we can observe nearly *13* frames of delay for some flips on Navi. [How] Apply the Raven workaround generically. When close enough to VUPDATE block cursor updates from occurring from the dc_stream_set_cursor_* helpers. This could perhaps be a little smarter by checking if there were pending updates or flips earlier in the frame on the HUBP side before applying the delay, but this should be fine for now. This fixes the kms_cursor_legacy test. Signed-off-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Sung Lee authored
[WHY & HOW] Viewport limit was set to 16 pixels due to an issue with MPO on small viewports. This restriction does not apply and the viewport limit can now be lowered. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Sung Lee authored
[WHY & HOW] If building scaling parameters fails, validation should also fail. Signed-off-by:
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Dmytro Laktyushkin authored
Currently RN SOC bounding box update assumes we will get at least 2 clock states from SMU. This isn't always true and because of special casing on first clock state we end up with low disp, dpp, dsc and phy clocks. This change removes the special casing allowing the first state to acquire correct clocks. Signed-off-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Check before programming the register since it isn't present on all IPs using this code. Signed-off-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Joshua Aberback authored
Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Anthony Koo authored
[Why] Some include paths don't need to have relative paths And some types missing [How] make some changes to headers and modify include path Signed-off-by:
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Nicholas Kazlauskas authored
[Why] The new metadata offset is located at the end of the firmware binary without any additional padding. Firmware state is currently larger than 1024 bytes so new firmware state will hang when trying to access any data above 1024 bytes. [How] Specify the correct offset based on legacy vs new loading method. Signed-off-by:
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Sung Lee authored
[WHY] If mode is not supported, pipe split should not be disabled. This may cause more modes to fail. [HOW] Check for mode support before disabling pipe split. This commit was previously reverted as it was thought to have problems, but those issues have been resolved. Signed-off-by:
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Aric Cyr authored
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Marek Olšák authored
This fixes GPU hangs due to cache coherency issues. Bump the driver version. Split out from the original patch. Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Tested-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by:
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Marek Olšák authored
This fixes GPU hangs due to cache coherency issues. v2: Split the version bump to a separate patch Signed-off-by:
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Marek Olšák authored
DCC_INDEPENDENT_128B is needed for displayble DCC on gfx10. SCANOUT is not needed by the kernel, but Mesa uses it. Signed-off-by:
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James Zhu authored
Wait for tiles off after unpause to fix transcode timeout issue. It is a work around. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Tiecheng Zhou authored
hwmgr->pm_en is initialized at hwmgr_hw_init. during amdgpu_device_init, there is amdgpu_asic_reset that calls to soc15_asic_reset (for V320 usecase, Vega10 asic), in which: 1) soc15_asic_reset_method calls to pp_get_asic_baco_capability (pm_en) 2) soc15_asic_baco_reset calls to pp_set_asic_baco_state (pm_en) pm_en is used in the above two cases while it has not yet been initialized So avoid using pm_en in the above two functions for V320 passthrough. Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Tiecheng Zhou <Tiecheng.Zhou@amd.com> Signed-off-by:
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Tiecheng Zhou authored
This reverts commit c5207876. The commit being reverted changed the wrong place, it should have changed in func get_asic_baco_capability. Reviewed-by:
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Joseph Greathouse authored
In order to surface the ASIC revision to user level, we want to put it into the HSA topology. This can be because different ASIC revisions may require user-level software to do different things (e.g. patch code for things that are changed in later hardware revisions). The ASIC revision from the hardware is maximum of 4 bits at this time, so put it into 4 of the open bits in the HSA capability. Then user-level software can use this capability information to know -- for each ASIC -- what revision-based things must be done. Signed-off-by:
Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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- 27 Apr, 2020 9 commits
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Jason Yan authored
The '>' expression itself is bool, no need to convert it to bool again. This fixes the following coccicheck warning: drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c:602:28-33: WARNING: conversion to bool not needed here Reviewed-by:
Jason Yan <yanaijie@huawei.com> Signed-off-by:
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Jason Yan authored
The '==' expression itself is bool, no need to convert it to bool again. This fixes the following coccicheck warning: drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c:455:70-75: WARNING: conversion to bool not needed here Reviewed-by:
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Jason Yan authored
The '>' expression itself is bool, no need to convert it to bool again. This fixes the following coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3004:68-73: WARNING: conversion to bool not needed here Reviewed-by:
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Guchun Chen authored
Due to hardware bug that when RSMU UMC index is disabled, clear EccErrCnt at the first UMC instance will clean up all other EccErrCnt registes from other instances at the same time. This will break the correctable error count log in EccErrCnt register once querying it. So decouple both to make error count query workable. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Guchun Chen authored
This makes consistent with other regsiters' access in this module. Signed-off-by:
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Evan Quan authored
CG/PG ungate is already performed in ip_suspend_phase1. Otherwise, the CG/PG ungate will be performed twice. That will cause gfxoff disablement is performed twice also on runpm enter while gfxoff enablemnt once on rump exit. That will put gfxoff into disabled state. Signed-off-by:
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Evan Quan authored
This sequence change should be safe as what did in ip_suspend_phase1 is to suspend DCE only. And this is a prerequisite for coming redundant cg/pg ungate dropping. Signed-off-by:
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Jonathan Kim authored
Driver steered p-state switching is designed for Vega20 only. Also simplify early return for temporary disable due to SMU FW bug. Signed-off-by:
Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by:
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Zheng Bin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2534:2-3: Unneeded semicolon Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Zheng Bin <zhengbin13@huawei.com> Signed-off-by:
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- 24 Apr, 2020 11 commits
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Colin Ian King authored
The variable option is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Colin Ian King authored
Currently the error returns paths are unlocking lock kiq->ring_lock however it seems this should be dev->gfx.kiq.ring_lock as this is the lock that is being locked and unlocked around the ring operations. This looks like a bug, but it's not. The kiq is just a local variable pointing to the same structure. Make it consistent. Signed-off-by:
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Colin Ian King authored
The variable ret is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: -
Yintian Tao authored
Wait for the oldest sequence on the ring to be signaled in order to make sure there will be no command overrun. v2: fix coding stype and remove abs operation v3: remove the initialization of variable r Signed-off-by:
Yintian Tao <yttao@amd.com> Reviewed-by:
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Monk Liu authored
to 5s to satisfy WHOLE GPU reset which need 3+ seconds to finish Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Acked-by:
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Monk Liu authored
because nv12 SRIOV support one vf mode Signed-off-by:
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Monk Liu authored
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Monk Liu authored
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Monk Liu authored
for ARCTURUS+ ASICS, we always support SW_SMU for bare-metal and for SRIOV one_vf_mode Signed-off-by:
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Monk Liu authored
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Monk Liu authored
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