1. 04 Jul, 2019 13 commits
  2. 03 Jul, 2019 21 commits
  3. 02 Jul, 2019 6 commits
    • Nicholas Piggin's avatar
      powerpc/64s/exception: remove bad stack branch · 0a882e28
      Nicholas Piggin authored
      The bad stack test in interrupt handlers has a few problems. For
      performance it is taken in the common case, which is a fetch bubble
      and a waste of i-cache.
      
      For code development and maintainence, it requires yet another stack
      frame setup routine, and that constrains all exception handlers to
      follow the same register save pattern which inhibits future
      optimisation.
      
      Remove the test/branch and replace it with a trap. Teach the program
      check handler to use the emergency stack for this case.
      
      This does not result in quite so nice a message, however the SRR0 and
      SRR1 of the crashed interrupt can be seen in r11 and r12, as is the
      original r1 (adjusted by INT_FRAME_SIZE). These are the most important
      parts to debugging the issue.
      
      The original r9-12 and cr0 is lost, which is the main downside.
      
        kernel BUG at linux/arch/powerpc/kernel/exceptions-64s.S:847!
        Oops: Exception in kernel mode, sig: 5 [#1]
        BE SMP NR_CPUS=2048 NUMA PowerNV
        Modules linked in:
        CPU: 0 PID: 1 Comm: swapper/0 Not tainted
        NIP:  c000000000009108 LR: c000000000cadbcc CTR: c0000000000090f0
        REGS: c0000000fffcbd70 TRAP: 0700   Not tainted
        MSR:  9000000000021032 <SF,HV,ME,IR,DR,RI>  CR: 28222448  XER: 20040000
        CFAR: c000000000009100 IRQMASK: 0
        GPR00: 000000000000003d fffffffffffffd00 c0000000018cfb00 c0000000f02b3166
        GPR04: fffffffffffffffd 0000000000000007 fffffffffffffffb 0000000000000030
        GPR08: 0000000000000037 0000000028222448 0000000000000000 c000000000ca8de0
        GPR12: 9000000002009032 c000000001ae0000 c000000000010a00 0000000000000000
        GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
        GPR20: c0000000f00322c0 c000000000f85200 0000000000000004 ffffffffffffffff
        GPR24: fffffffffffffffe 0000000000000000 0000000000000000 000000000000000a
        GPR28: 0000000000000000 0000000000000000 c0000000f02b391c c0000000f02b3167
        NIP [c000000000009108] decrementer_common+0x18/0x160
        LR [c000000000cadbcc] .vsnprintf+0x3ec/0x4f0
        Call Trace:
        Instruction dump:
        996d098a 994d098b 38610070 480246ed 48005518 60000000 38200000 718a4000
        7c2a0b78 3821fd00 41c20008 e82d0970 <0981fd00> f92101a0 f9610170 f9810178
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      0a882e28
    • Nicholas Piggin's avatar
      powerpc/tm: update comment about interrupt re-entrancy · f30a5e68
      Nicholas Piggin authored
      Since the system reset interrupt began to use its own stack, and
      machine check interrupts have done so for some time, r1 can be
      changed without clearing MSR[RI], provided no other interrupts
      (including SLB misses) are taken.
      
      MSR[RI] does have to be cleared when using SCRATCH0, however.
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      f30a5e68
    • Nicholas Piggin's avatar
      powerpc/64s/exception: move SET_SCRATCH0 into EXCEPTION_PROLOG_0 · d7fb34c7
      Nicholas Piggin authored
      No generated code change.
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      d7fb34c7
    • Nicholas Piggin's avatar
      powerpc/64s/exception: denorm handler use standard scratch save macro · 904f81f3
      Nicholas Piggin authored
      Although the 0x1500 interrupt only applies to bare metal, it is better
      to just use the standard macro for scratch save.
      
      Runtime code path remains unchanged (due to instruction patching).
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      904f81f3
    • Nicholas Piggin's avatar
    • Nicholas Piggin's avatar
      powerpc/64s/exception: add dar and dsisr options to exception macro · 5312c494
      Nicholas Piggin authored
      Some exception entry requires DAR and/or DSISR to be saved into the
      paca exception save area. Add options to the standard exception
      macros for these.
      
      Generated code changes slightly due to code structure.
      
      -     554:      a6 02 72 7d     mfdsisr r11
      -     558:      a8 00 4d f9     std     r10,168(r13)
      -     55c:      b0 00 6d 91     stw     r11,176(r13)
      +     554:      a8 00 4d f9     std     r10,168(r13)
      +     558:      a6 02 52 7d     mfdsisr r10
      +     55c:      b0 00 4d 91     stw     r10,176(r13)
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      5312c494