- 27 May, 2024 36 commits
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Dmitry Baryshkov authored
The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: 5a814af5 ("arm64: dts: qcom: sm6350: Add UFS nodes") Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-8-f1fd15c33fb3@linaro.orgSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Dmitry Baryshkov authored
The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: 97e563bf ("arm64: dts: qcom: sm6115: Add basic soc dtsi") Signed-off-by:
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Dmitry Baryshkov authored
The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: cc16687f ("arm64: dts: qcom: sdm845: add UFS controller") Signed-off-by:
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Dmitry Baryshkov authored
The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: 8575f197 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by:
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Dmitry Baryshkov authored
The DT schema doesn't have a fallback compatible for qcom,sc7180-qmp-ufs-phy. Drop it from the dtsi too. Fixes: 858536d9 ("arm64: dts: qcom: sc7180: Add UFS nodes") Signed-off-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-4-f1fd15c33fb3@linaro.orgSigned-off-by:
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Mrinmay Sarkar authored
Add ep pcie dtsi node for pcie1 controller found on sa8775p platform. It supports gen4 and x4 link width. Limiting the speed to Gen3 due to stability issue with Gen4. Signed-off-by:
Mrinmay Sarkar <quic_msarkar@quicinc.com> Link: https://lore.kernel.org/r/1714494089-7917-3-git-send-email-quic_msarkar@quicinc.comSigned-off-by:
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Mrinmay Sarkar authored
Add ep pcie dtsi node for pcie0 controller found on sa8775p platform. It supports gen4 and x2 link width. Limiting the speed to Gen3 due to stability issues. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1714492540-15419-4-git-send-email-quic_msarkar@quicinc.comSigned-off-by:
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Krzysztof Kozlowski authored
Node names should not have vendor prefixes. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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Kaushal Kumar authored
Add SMP2P node for the SDX75 platform to communicate with the modem. Signed-off-by:
Kaushal Kumar <quic_kaushalk@quicinc.com> Link: https://lore.kernel.org/r/20240426112837.17478-1-quic_kaushalk@quicinc.comSigned-off-by:
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Rohit Agarwal authored
Add AOSS channel devicetree node for Qcom's SDX75 SoC. Signed-off-by:
Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/20240426055326.3141727-7-quic_rohiagar@quicinc.comSigned-off-by:
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Rohit Agarwal authored
Add TCSR register space devicetree node for accessing different status registers. Signed-off-by:
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Rohit Agarwal authored
Add IPCC devicetree node to Qcom's SDX75 platform. Signed-off-by:
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Neil Armstrong authored
Add path of the GPU firmware for the SM8650-HDK board Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
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Raymond Hackley authored
Add subnode usb_con: extcon for SM5502 / SM5504 MUIC, which will be used for RT5033 charger. Signed-off-by:
Raymond Hackley <raymondhackley@protonmail.com> Reviewed-by:
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Raymond Hackley authored
The phones listed below have Richtek RT5033 PMIC and charger. Add them to the device trees. - Samsung Galaxy A3/A5/A7 2015 - Samsung Galaxy E5/E7 - Samsung Galaxy Grand Max Signed-off-by:
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Tengfei Fan authored
Add a description of a SM4450 cpufreq-epss controller,add references to it from CPU nodes and make EPSS a supplyer of clocks for the CPUs. Signed-off-by:
Tengfei Fan <quic_tengfan@quicinc.com> Reviewed-by:
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Viken Dadhaniya authored
For IDP variant, GPIO 20/21 is used by camera use case and camera driver is not able acquire these GPIOs as it is acquired by UART5 driver as RTS/CTS pin. UART5 is designed for debug UART for all the board variants of the sc7280 chipset and RTS/CTS configuration is not required for debug uart usecase. Remove CTS/RTS configuration for UART5 instance and change compatible string to debug UART. Remove overwriting compatible property from individual target specific file as it is not required. Fixes: 38cd93f4 ("arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT node") Signed-off-by:
Viken Dadhaniya <quic_vdadhani@quicinc.com> Link: https://lore.kernel.org/r/20240424075853.11445-1-quic_vdadhani@quicinc.comSigned-off-by:
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Viken Dadhaniya authored
Enable gpi-dma0, gpi-dma1 and qupv3_id_1 nodes for buses usecase on RB3gen2. Signed-off-by:
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Neil Armstrong authored
The SM8650-HDK is an embedded development platforms for the Snapdragon 8 Gen 3 SoC aka SM8650, with the following features: - Qualcomm SM8650 SoC - 16GiB On-board LPDDR5 - On-board WiFi 7 + Bluetooth 5.3/BLE - On-board UFS4.0 - M.2 Key B+M Gen3x2 PCIe Slot - HDMI Output - USB-C Connector with DP Almode & Audio Accessory mode - Micro-SDCard Slot - Audio Jack with Playback and Microphone - 2 On-board Analog microphones - 2 On-board Speakers - 96Boards Compatible Low-Speed and High-Speed connectors [1] - For Camera, Sensors and external Display cards - Compatible with the Linaro Debug board [2] - SIM Slot for Modem - Debug connectors - 6x On-Board LEDs Product Page: [3] [1] https://www.96boards.org/specifications/ [2] https://git.codelinaro.org/linaro/qcomlt/debugboard [3] https://www.lantronix.com/products/snapdragon-8-gen-3-mobile-hardware-development-kit/Reviewed-by:
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Tested-by:
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Neil Armstrong authored
Document the Qualcomm SM8650 based HDK (Hardware Development Kit) embedded development platform designed by Qualcomm and sold by Lantronix [1]. [1] https://www.lantronix.com/products/snapdragon-8-gen-3-mobile-hardware-development-kit/Reviewed-by:
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Manivannan Sadhasivam authored
Qcom SoCs doesn't support legacy PCI, but only PCIe. So use the correct node name for the controller instances. Reviewed-by:
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Neil Armstrong authored
The PCIe Gen4x2 PHY found in the SM8650 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Remove the dummy pcie-1-phy-aux-clk clock and now the pcie1_phy exposes 2 clocks, properly add the pcie1_phy provided clocks to the Global Clock Controller (GCC) node clocks inputs. Reviewed-by:
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Neil Armstrong authored
The PCIe Gen4x2 PHY found in the SM8550 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Remove the dummy pcie-1-phy-aux-clk clock and now the pcie1_phy exposes 2 clocks, properly add the pcie1_phy provided clocks to the Global Clock Controller (GCC) node clocks inputs. Reviewed-by:
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Neil Armstrong authored
The PCIe Gen4x2 PHY found in the SM8450 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Now the pcie1_phy exposes 2 clocks, properly add the pcie1_phy provided clocks to the Global Clock Controller (GCC) node clocks inputs. Reviewed-by:
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Dmitry Baryshkov authored
The usb-role-switch property doesn't make sense for the USB hosts which are fixed to the host USB data mode. Delete usb-role-switch property from these hosts. Signed-off-by:
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Dmitry Baryshkov authored
The usb-role-switch property doesn't make sense for the USB hosts which are fixed to either host or peripheral USB data mode. Delete usb-role-switch property being present in SoC dtsi. Signed-off-by:
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Dmitry Baryshkov authored
The lanes from the USB-C SS port are connected to the combo USB+DP QMP PHY rather than the SS port of the USB controller. Move the connection endpoint to the QMP PHY out port. Signed-off-by:
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Dmitry Baryshkov authored
The orientation-switch of the USB+DP QMP PHY is not a property of the board, it is a design property of the QMP PHY itself. Move the property from board DTS to SoC DTSI. Signed-off-by:
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Dmitry Baryshkov authored
The orientation-switch of the USB+DP QMP PHY is not a property of the board, it is a design property of the QMP PHY itself. Move the property from board DTS to SoC DTSI. Signed-off-by:
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Dmitry Baryshkov authored
The orientation-switch of the USB+DP QMP PHY is not a property of the board, it is a design property of the QMP PHY itself. Move the property from board DTS to SoC DTSI. Signed-off-by:
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Dmitry Baryshkov authored
The orientation-switch of the USB+DP QMP PHY is not a property of the board, it is a design property of the QMP PHY itself. Move the property from board DTS to SoC DTSI. Signed-off-by:
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Dmitry Baryshkov authored
Move the graph connection between USB host, USB SS PHY and DP port to the SoC dtsi file. They are linked in hardware in this way. Signed-off-by:
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Dmitry Baryshkov authored
Move the graph connection between USB host, USB SS PHY and DP port to the SoC dtsi file. They are linked in hardware in this way. Signed-off-by:
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Dmitry Baryshkov authored
Move the graph connection between USB host, USB SS PHY and DP port to the SoC dtsi file. They are linked in hardware in this way. Signed-off-by:
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Dmitry Baryshkov authored
Move the graph connection between USB host, USB SS PHY and DP port to the SoC dtsi file. They are linked in hardware in this way. Signed-off-by:
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Dmitry Baryshkov authored
Move the graph connection between USB host, USB SS PHY and DP port to the SoC dtsi file. They are linked in hardware in this way. Signed-off-by:
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- 26 May, 2024 4 commits
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Barnabás Czémán authored
Add reset for display subsystem, make sure it gets properly reset. Signed-off-by:
Barnabás Czémán <trabarni@gmail.com> Reviewed-by:
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Bjorn Andersson authored
The interconnects property was clearly copy-pasted between the 4 PCIe controllers, giving all four the cpu-pcie path destination of SLAVE_0. The four ports are all associated with CN0, but update the property for correctness sake. Fixes: d20b6c84 ("arm64: dts: qcom: sc8180x: Add PCIe instances") Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by:
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Bjorn Andersson authored
The #power-domains property is no longer accepted according to the AOSS QMP binding, drop it from the node. Signed-off-by:
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Bjorn Andersson authored
The IPA BCM is already exposed by clk-rpmh, remove the interconnect node for the same. Signed-off-by:
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