- 26 Sep, 2017 40 commits
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Yongqiang Sun authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
Harry Wentland <Harry.Wentland@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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xhdu authored
Leave hardcoded if no ContainerId provided by DM. Signed-off-by:
Duke Du <Duke.Du@amd.com> Acked-by:
Charlene Liu <Charlene.Liu@amd.com> Signed-off-by:
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Charlene Liu authored
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Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
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Charlene Liu authored
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Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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Charlene Liu authored
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Leon Elazar authored
1. Locking all pipes before doing any changes 2. Applying surface for both top and bottom pipes Signed-off-by:
Leon Elazar <leon.elazar@amd.com> Acked-by:
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Andrey Grodzovsky authored
Signed-off-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Reviewed-by:
Jordan Lazare <Jordan.Lazare@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
This will return back MAX cursor size for given ASIC. Signed-off-by:
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Andrey Grodzovsky authored
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Andrey Grodzovsky authored
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Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
ret value in amdgpu_dm_atomic_check was not rest to EINVAL after drm_atomic_add_affected_planes and by this making any subsequent validation failure pass when returning to atomic_check. v2: Add WARN_ON print for dc_commit_streams in amdgpu_dm_atomic_commit_tail since this should never fail. Signed-off-by:
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Tony Cheng authored
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Tony Cheng authored
- also some clean up Signed-off-by:
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Yongqiang Sun authored
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Dmytro Laktyushkin authored
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Tony Cheng authored
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Leon Elazar authored
1. Adding the ability to update the stream parameters during FULL_UPDATE type Signed-off-by:
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Dmytro Laktyushkin authored
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Logatharshan Thothiralingam authored
[Problem] VSR greyed out [Root cause] When converting fractions, we were using the integer function, which let to a large display clock and the view was not supported [Solution] Change the integer to fraction functions Signed-off-by:
Logatharshan Thothiralingam <logatharshan.thothiralingam@amd.com> Acked-by:
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Leon Elazar authored
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Alex Deucher authored
Add the DC display module to drive the DCE12 IP on vega10. Signed-off-by: -
Alex Deucher authored
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Jordan Lazare authored
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Charlene Liu authored
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Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Alex Deucher authored
This wires DCE12 support into DC and enables it. Signed-off-by:
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Harry Wentland authored
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Harry Wentland authored
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Harry Wentland authored
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Harry Wentland authored
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Harry Wentland authored
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Rex Zhu authored
Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
Viewport would be incorrectly adjusted when surface was used for multiple displays Signed-off-by:
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Jordan Lazare authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Zeyu Fan authored
Signed-off-by:
Zeyu Fan <Zeyu.Fan@amd.com> Acked-by:
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Andrey Grodzovsky authored
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Yongqiang Sun authored
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Yongqiang Sun authored
Issue: In case of two 4K@60 + one non-4k monitor, when unplug non-4k monitor, the remain two 4k monitor don't work properly. Reason: In that case, two 4k use two pipes and no split, when unplug happens, those two monitor will use 4 pipes and split, but on that time, frontend is not programed properly. Solution: After programed backend, front end should be programmed as per new pipe setting. Signed-off-by:
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