- 21 Nov, 2023 1 commit
-
-
Imre Deak authored
On UHBR links the PBN divider is a fractional number, accordingly store it in fixed point format. For now drm_dp_get_vc_payload_bw() always returns a whole number and all callers will use only the integer part of it which should preserve the current behavior. The next patch will fix drm_dp_get_vc_payload_bw() for UHBR rates returning a fractional number for those (also accounting for the channel coding efficiency correctly). Cc: Lyude Paul <lyude@redhat.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Wayne Lin <wayne.lin@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> [Rebased changes in dm_helpers_construct_old_payload() on drm-intel-next] Signed-off-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231116131841.1588781-2-imre.deak@intel.com
-
- 20 Nov, 2023 4 commits
-
-
Ville Syrjälä authored
IVB Bspec says: "Frame Buffer Compression is only supported with memory surfaces of 4096 lines or less and pipe source sizes of 4096 pixels by 2048 lines or less. " so seems like we should be able to bump the offset+size limit to at least 4kx4k. Make it so. Signed-off-by:
Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
-
Ville Syrjälä authored
FBC on icl+ should supposedly be fine with surface sizes up to 8kx4k. Bump up the limit. Signed-off-by:
-
Ville Syrjälä authored
Do separate checks for the visible plane size vs. the surface size (which I take to mean offset+size). For now both use the same max w/h, but we can relax the surface size limits as a followup. Signed-off-by:
-
Ville Syrjälä authored
Unfortunately even the HPD based detection added in commit cfe5bdfb ("drm/i915: Check HPD live state during eDP probe") fails to detect that the VBT's eDP/DDI-A is a ghost on Asus B360M-A (CFL+CNP). On that board eDP/DDI-A has its HPD asserted despite nothing being actually connected there :( The straps/fuses also indicate that the eDP port is present. So if one boots with a VGA monitor connected the eDP probe will mistake the DP->VGA converter hooked to DDI-E for an eDP panel on DDI-A. As a last resort check what kind of DP device we've detected, and if it looks like a DP->VGA converter then conclude that the eDP port should be ignored. Cc: stable@vger.kernel.org Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9636 Fixes: cfe5bdfb ("drm/i915: Check HPD live state during eDP probe") Signed-off-by:
Jani Nikula <jani.nikula@intel.com>
-
- 17 Nov, 2023 4 commits
-
-
Jani Nikula authored
vlv_dpio_read() and vlv_dpio_write() really operate on the phy, not pipe. Passing the pipe instead of the phy as parameter is supposed to be a convenience, but when the caller has the phy, it becomes an inconvenience. See e.g. chv_dpio_cmn_power_well_enable() and assert_chv_phy_powergate(). Figure out the phy in the callers, and pass phy to the dpio functions. v2: retract one overzealous pipe->phy change (Ville) Reviewed-by:
-
Jani Nikula authored
Add a helper with better typing and handing for bogus input, and better in line with vlv_dig_port_to_channel(), vlv_dig_port_to_phy(), and vlv_pipe_to_channel(). Reviewed-by:
-
Jani Nikula authored
Considering what the functions do, intel_dpll.c is a more suitable location, and lets us make some functions static while at it. This also means intel_display.c no longer does any DPIO access. Reviewed-by:
-
Jani Nikula authored
Like the comment says, /* Grouping using anonymous structs. Keep sorted. */ Stick to it. Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231114155528.96935-1-jani.nikula@intel.com
-
- 16 Nov, 2023 1 commit
-
-
Animesh Manna authored
Refactor DSB implementation to be compatible with Xe driver. v1: RFC version. v2: Make intel_dsb structure opaque from external usage. [Jani] v3: Rebased on latest. v4: - Add boundary check in dsb_buffer_memset(). [Luca] - Use size_t instead of u32. [Luca] v5: WARN_ON() added for out of boudary case with some optimization. [Luca] v6: Rebased on latest and fix a rebase-miss. Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Luca Coelho <luciano.coelho@intel.com> Signed-off-by:
Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231110032518.3564279-1-animesh.manna@intel.com
-
- 15 Nov, 2023 3 commits
-
-
Imre Deak authored
Convert crtc_state->pipe_bpp to U6.4 format as expected by the rest of the function. Fixes: 59a266f0 ("drm/i915/display: Store compressed bpp in U6.4 format") Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Sui Jingfeng <suijingfeng@loongson.cn> Reviewed-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:
-
Animesh Manna authored
Add debugfs support which will print source and sink status per connector basis. Existing i915_psr_status and i915_psr_sink_status will be used to get the source and sink status of panel replay. v1: Initial version. [rb-ed by Arun] v2: Added check for DP 2.0 and connector type in connector_debugfs_add(). v3: Optimization and cosmetic changes. [Jouni] Cc: Jouni Högander <jouni.hogander@intel.com> Cc: Arun R Murthy <arun.r.murthy@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by:
Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231108072303.3414118-7-animesh.manna@intel.com
-
Vinod Govindapillai authored
FIFO underruns are observed when FBC is enabled on plane 2 or plane 3. Recommended WA is to update the FBC enabling sequence. The plane binding register bits need to be updated separately before programming the FBC enable bit. Bspec: 74151 Reviewed-by: Mika Kahola <mika.kahola@intel.com> #v3 Signed-off-by:
Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by:
Mika Kahola <mika.kahola@intel.com> Signed-off-by:
-
- 14 Nov, 2023 10 commits
-
-
Imre Deak authored
At least a Realtek DP branch device with the OUI 00-e0-4c dev-ID Dp1.4 HW-rev 1.0 SW-rev 131.1 device identification doesn't report detecting the FEC decoding start symbol. Tune down the corresponding error to a debug message. Reviewed-by:
-
Mika Kahola authored
At least one TGL had regression when using u8 types for entry setup frames calculation. So, let's switch to use ints instead. intel_psr_entry_setup_frames() function expects to return u8 but since in case of error the error code -ETIME is returned. This doesn't fit into u8 and hence the return value is not as expected. Fixes: 2b981d57 ("drm/i915/display: Support PSR entry VSC packet to be transmitted one frame earlier") Signed-off-by:
-
Swati Sharma authored
If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff compressed bpp is fractional. Continue if the computed compressed bpp turns out to be a integer. v2: -Use helpers for fractional, integral bits of bits_per_pixel. (Suraj) -Fix comment (Suraj) Signed-off-by:
Swati Sharma <swati2.sharma@intel.com> Signed-off-by:
Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by:
Sui Jingfeng <suijingfeng@loongson.cn> Link: https://patchwork.freedesktop.org/patch/msgid/20231110101020.4067342-9-ankit.k.nautiyal@intel.com
-
Swati Sharma authored
DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show to depict sink's precision. Also, new debugfs entry is created to enforce fractional bpp. If Force_DSC_Fractional_BPP_en is set then while iterating over output bpp with fractional step size we will continue if output_bpp is computed as integer. With this approach, we will be able to validate DSC with fractional bpp. v2: Add drm_modeset_unlock to new line(Suraj) Signed-off-by:
Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by:
-
Ankit Nautiyal authored
This patch adds support to iterate over compressed output bpp as per the fractional step, supported by DP sink. v2: -Avoid ending up with compressed bpp, same as pipe bpp. (Stan) Signed-off-by:
-
Vandita Kulkarni authored
Consider the fractional bpp while reading the qp values. v2: Use helpers for fractional, integral bits of bits_per_pixel. (Suraj) Signed-off-by:
Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by:
-
Ankit Nautiyal authored
MTL+ supports fractional compressed bits_per_pixel, with precision of 1/16. This compressed bpp is stored in U6.4 format. Accommodate the precision during calculation of transfer unit data for hblank_early calculation. v2: -Fix tu_data calculation while dealing with U6.4 format. (Stan) v3: -Use BPP_X16_FMT to print vdsc bpp. Signed-off-by:
-
Ankit Nautiyal authored
MTL+ supports fractional compressed bits_per_pixel, with precision of 1/16. This compressed bpp is stored in U6.4 format. Accommodate this precision while computing m_n values. v1: Replace the computation of 'data_clock' with 'data_clock = DIV_ROUND_UP(data_clock, 16).' (Sui Jingfeng). v2: Rebase and pass bits_per_pixel in U6.4 format. Signed-off-by:
-
Ankit Nautiyal authored
DSC parameter bits_per_pixel is stored in U6.4 format. The 4 bits represent the fractional part of the bpp. Currently we use compressed_bpp member of dsc structure to store only the integral part of the bits_per_pixel. To store the full bits_per_pixel along with the fractional part, compressed_bpp is changed to store bpp in U6.4 formats. Intergral part is retrieved by simply right shifting the member compressed_bpp by 4. v2: -Use to_bpp_int, to_bpp_frac_dec, to_bpp_x16 helpers while dealing with compressed bpp. (Suraj) -Fix comment styling. (Suraj) v3: -Add separate file for 6.4 fixed point helper(Jani, Nikula) -Add comment for magic values(Suraj) v4: -Fix checkpatch warnings caused by renaming(Suraj) v5: -Rebase. -Use existing helpers for conversion of bpp_int to bpp_x16 and vice versa. Signed-off-by:
-
Ankit Nautiyal authored
Add helper to get the DSC bits_per_pixel precision for the DP sink. Signed-off-by:
Maxime Ripard <mripard@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20231110101020.4067342-2-ankit.k.nautiyal@intel.com
-
- 13 Nov, 2023 1 commit
-
-
Mika Kahola authored
Add state verification for C20 as we have one for C10. V2: Use abstractation of HW readout (Gustavo) Drop MPLLA/B from message for TX and CMN parameters (Gustavo) Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> (v1,v2) Signed-off-by:
-
- 11 Nov, 2023 2 commits
-
-
Jani Nikula authored
The bug filing documentation has been moved from the gitlab wiki to gitlab pages at https://drm.pages.freedesktop.org/intel-docs/. Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by:
-
Jani Nikula authored
The 01.org page has ceased to exist, and the relevant documentation is now hosted at https://drm.pages.freedesktop.org/intel-docs/ Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by:
-
- 10 Nov, 2023 7 commits
-
-
Jani Nikula authored
Reduce the function calls by reusing ->decrypt. Reviewed-by:
-
Jani Nikula authored
Centralize the conditions in a function. Reviewed-by:
-
Animesh Manna authored
TRANS_DP2_CTL register is programmed to enable panel replay from source and sink is enabled through panel replay dpcd configuration address. Bspec: 1407940617 v1: Initial version. v2: - Use pr_* flags instead psr_* flags. [Jouni] - Remove intel_dp_is_edp check as edp1.5 also has panel replay. [Jouni] v3: Cover letter updated and selective fetch condition check is added before updating its bit in PSR2_MAN_TRK_CTL register. [Jouni] v4: Selective fetch related PSR2_MAN_TRK_CTL programmming dropped. [Jouni] v5: Added PSR2_MAN_TRK_CTL programming as needed for Continuous Full Frame (CFF) update. v6: Rebased on latest. Note: Initial plan is to enable panel replay in full-screen live active frame update mode. In a incremental approach panel replay will be enabled in selctive update mode if there is any gap in curent implementation. Cc: Jouni Högander <jouni.hogander@intel.com> Cc: Arun R Murthy <arun.r.murthy@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by:
-
Animesh Manna authored
Due to similarity panel replay dpcd initialization got added in psr function which is specific for edp panel. This patch enables panel replay initialization for dp connector. Cc: Jouni Högander <jouni.hogander@intel.com> Cc: Arun R Murthy <arun.r.murthy@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by:
-
Animesh Manna authored
Modify existing PSR implementation to enable panel replay feature of DP 2.0 which is similar to PSR feature of EDP panel. There is different DPCD address to check panel capability compare to PSR and vsc sdp header is different. v1: Initial version. v2: - Set source_panel_replay_support flag under HAS_PANEL_REPLAY() condition check. [Jouni] - Code restructured around intel_panel_replay_init and renamed to intel_panel_replay_init_dpcd. [Jouni] - Remove the initial code modification around has_psr2 flag. [Jouni] - Add CAN_PANEL_REPLAY() in intel_encoder_can_psr which is used to enable in intel_psr_post_plane_update. [Jouni] v3: - Initialize both psr and panel-replay. [Jouni] - Initialize both panel replay and psr if detected. [Jouni] - Refactoring psr function by introducing _psr_compute_config(). [Jouni] - Add check for !is_edp while deriving source_panel_replay_support. [Jouni] - Enable panel replay dpcd initialization in a separate patch. [Jouni] v4: - HAS_PANEL_REPLAY() check not needed during sink capability check. [Jouni] - Set either panel replay source support or psr. [Jouni] v5: - HAS_PANEL_REPLAY() removed and use HAS_DP20() instead. [Jouni] - Move psr related code to intel_psr.c. [Jani] - Reset sink_panel_replay_support flag during disconnection. [Jani] v6: return statement restored which is removed by misatke. [Jouni] v7: cosmetic changes. [Arun] Cc: Jouni Högander <jouni.hogander@intel.com> Cc: Arun R Murthy <arun.r.murthy@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by:
-
Jouni Högander authored
This patch is preparing adding panel replay specific dpcd init. Cc: Arun R Murthy <arun.r.murthy@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by:
-
Animesh Manna authored
Add DPCD register definition for discovering, enabling and checking status of panel replay of the sink. Cc: Jouni Högander <jouni.hogander@intel.com> Cc: Arun R Murthy <arun.r.murthy@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Acked-by:
-
- 08 Nov, 2023 7 commits
-
-
Ville Syrjälä authored
Just use a simple {} to zero initialize arrays/structs instead of the hodgepodge of stuff we are using currently. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Zhi Wang <zhi.a.wang@intel.com> Signed-off-by: -
Ville Syrjälä authored
Perform all the intel_pre_update_crtc() stuff for all pipes first, and only then do the intel_update_crtc() vblank evasion stuff for every pipe back to back. This should make it more likely that the plane updates from multiple pipes happen on the same frame (assuming the pipes are running in sync, eg. due to bigjoiner or port sync). Signed-off-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
-
Ville Syrjälä authored
Split intel_update_crtc() into two parts such that the first part performs all the non-vblank evasion preparatory stuff, and the second part just does the vblank evasion stuff. For now we just call these back to back so that there is no funcitonal change. Signed-off-by:
-
Ville Syrjälä authored
Since commit 7de5b6b5 ("drm/i915: Don't flag both full modeset and fastset at the same time") intel_crtc_needs_fastset() and intel_crtc_needs_modeset() have been mutually exclusive. Drop the redundant check. Signed-off-by:
-
Stanislav Lisovskiy authored
Currently we seem to be using wrong DPCD register for reading compressed bpps, reading min/max input bpc instead of compressed bpp. Fix that, so that we now apply min/max compressed bpp limitations we get from DP Spec Table 2-157 DP v2.0 and/or correspondent DPCD register DP_DSC_MAX_BITS_PER_PIXEL_LOW/HIGH. This might also allow us to get rid of an ugly compressed bpp recalculation, which we had to add to make some MST hubs usable. v2: - Fix operator precedence v3: - Added debug info about compressed bpps v4: - Don't try to intersect Sink input bpp and compressed bpps. v5: - Decrease step while looking for suitable compressed bpp to accommodate. v6: - Use helper for getting min and max compressed_bpp (Ankit) v7: - Fix checkpatch warning (Ankit) Signed-off-by: -
Imre Deak authored
After the previous patch the BW limits on the whole MST topology will be checked after computing the state for all the streams in the topology. Accordingly remove the check during the stream's encoder compute config step, to prevent failing an atomic commit due to a BW limit, if this can be resolved only by reducing the BW of other streams on the same MST link. Reviewed-by:
-
Imre Deak authored
At the moment modesetting a stream CRTC will fail if the stream's BW along with the current BW of all the other streams on the same MST link is above the total BW of the MST link. Make the BW sharing more dynamic by trying to reduce the link bpp of one or more streams on the MST link in this case. When selecting a stream to reduce the BW for, take into account which link segment in the MST topology ran out of BW and which streams go through this link segment. For instance with A,B,C streams in the same MST topology A and B may share the BW of a link segment downstream of a branch device, stream C not downstream of the branch device, hence not affecting this BW. If this link segment's BW runs out one or both of stream A/B's BW will be reduced until their total BW is within limits. While reducing the link bpp for a given stream DSC may need to be enabled for it, which requires FEC on the whole MST link. Check for this condition and recompute the state for all streams taking the FEC overhead into account (on 8b/10b links). v2: - Rebase on s/min_bpp_pipes/min_bpp_reached_pipes/ change. Reviewed-by:
-
